AN2168 Freescale Semiconductor / Motorola, AN2168 Datasheet - Page 2

• Manufacturer Part Number: AN2168
• Description: ColdFire Microprocessor DMA Controller Application Note
• Manufacturer: Freescale Semiconductor / Motorola

Application Note
What Is a DMA Controller?
Why Use the DMA Controller?
What Do DMA Bus Cycles Look Like?
2
The DMA controller allows large blocks of data to be transferred without
intervention from the CPU (central processor unit). Once the DMA
registers have been programmed, a transfer can be started that will
relocate data from one memory location to another or write data to/from
a peripheral.
When the DMA transfers data, it isn’t necessarily faster than using a
series of move instructions to relocate the data instead. In fact, the
timing for the bus cycle usually will be the same regardless of whether
the DMA or the core initiated the access. However, the DMA can
increase the overall performance of the system by freeing up the core to
execute code that is stored in cache or the on-chip SRAM (standby RAM
module). This has the inherent drawback that cache coherency is not
maintained when using the DMA, and the DMA cannot transfer data to
or from the on-chip SRAM.
The ColdFire user’s manuals don’t show DMA-specific timings for full
bus cycles, because there isn't a difference in the timing for a bus cycle
initiated by the core and a bus cycle initiated by the DMA.
When performing a DMA transfer, as long as the alternate master (AM)
bit for the corresponding chip select or DRAMC register is cleared, the
DMA address can still “hit” in the associated chip select or DRAM
(dynamic RAM) region. Therefore, the bus cycles will appear the same
as a non-DMA (ColdFire core) access to the same address since the
timing (wait states, CAS latency, etc.) will be controlled by the same
register settings. The timing, control signals, and strobes will be the
same, only the transfer type and transfer modifier information will be
different. So if the DMA source or destination address “hits” in a chip
select space, then the chip select control registers will define the bus
cycle (wait states, bursting, etc.).
MOTOROLA
AN2168