AN2168 Freescale Semiconductor / Motorola, AN2168 Datasheet - Page 13

• Manufacturer Part Number: AN2168
• Description: ColdFire Microprocessor DMA Controller Application Note
• Manufacturer: Freescale Semiconductor / Motorola

AN2168
MOTOROLA
Figure 7. Cycle Steal Transfer Using External Request Mode — 2
Figure 6
the assertion of DREQ. After DREQ asserts, the processor completes
the current bus cycle and grants mastership of the external bus to the
DMA channel. Since the DMA is programmed for cycle steal mode, there
is just one read and one write phase. The basic DMA transfer timing is
the same as shown in
DMA transfer completes, the BCR is decremented by two. Bus
mastership is then returned to the core and a normal mode bus cycle
starts at cursor 2.
Figure 7
beginning of the same normal mode access, as shown in
Again the DREQ signal is asserted to indicate an external DMA request
to the ColdFire. Once the DMA channel gains mastership, another read
and write phase is started (cursor 1). After the write phase is complete,
the BCR decrements by two again, clearing the BCR. This signals the
end of the entire DMA transfer and the DONE bit in the DSR is set.
Finally, bus mastership returns to the core and a normal mode access is
started.
shows the first word transfer of the DMA cycle. Cursor 1 marks
shows the transfer of the second word. Cursor 2 marks the
Dual Address Mode Example
1. After the first
Application Note
Figure
Request Modes
6.
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