AN2168 Freescale Semiconductor / Motorola, AN2168 Datasheet - Page 18

• Manufacturer Part Number: AN2168
• Description: ColdFire Microprocessor DMA Controller Application Note
• Manufacturer: Freescale Semiconductor / Motorola

Application Note
DMA and Bus Prioritization (Latency Issues)
Setting Up Interrupts for the DMA
Programming
the DIVR
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There are a couple of prioritization schemes that should be taken into
account when using the DMA. The first is the prioritization between the
ColdFire core and the DMA module. The ColdFire has an internal arbiter
that determines when the core or DMA should be granted access to the
external bus. The user can change the arbiter settings by programming
the MPARK register. If a system has too much delay between the
request for a DMA transfer and the DMA bus cycle, then the latency
might be reduced by reprogramming the MPARK register to give the
DMA channel priority over the core. The actual settings and arbitration
schemes vary from part to part, so refer to the SIM (system integration
module) section of the appropriate user’s manual for more details.
Determining the correct vector number to use is the main concern when
using interrupts for on-chip resources. For the ColdFire DMA module,
there are two options for generating an interrupt vector number in
response to an interrupt acknowledge (IACK) cycle:
The first option is to program the DMA interrupt vector register (DIVR)
with the hex interrupt vector. The vector chosen should be one of the
ColdFire user-defined interrupts (vectors 64–255). When an IACK cycle
for a DMA interrupt occurs, the DMA will return the value in the DIVR.
Then the processor will start the exception handling process by building
the exception stack frame and fetching the vector table entry specified
by the DIVR.
Refer to
•
•
Programming the DIVR
Using the autovector feature
DMA Interrupt Example
for a software example.
MOTOROLA
AN2168