AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet
AN2797
Related parts for AN2797
AN2797 Summary of contents
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... L3 cache, the L3 cache features of the MPC745x devices are not mentioned. © Freescale Semiconductor, Inc., 2004. All rights reserved. Rev. 1.0, 10/2004 Contents 1. Scope and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Feature Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. 7447A Specific Features . . . . . . . . . . . . . . . . . . . . . . 11 4. Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Hardware Considerations . . . . . . . . . . . . . . . . . . . . . 25 AN2797 ...
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Feature Overview 2 Feature Overview There are many differences between the IBM 750GX and MPC7447A devices beyond the clear differences of the core complex. This chapter covers the differences between the cores and then other areas of interest including the ...
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Migrating from IBM 750GX to MPC7447A, Rev. 1.0 Freescale Semiconductor Figure 2. MPC 7447A Feature Overview 3 ...
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Feature Overview 2.1.1 Integer Units Fixed unit 1 (FXU1) and Fixed unit 2 (FXU2) are the complex and simple integer units respectively. The multiply and divide instructions of FXU1 are multi-cycle, while all other operations are completed in a single ...
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Branch Processing Unit The branch processing unit found in the IBM 750GX can process one branch while resolving two speculative branches per cycle. It uses a 512-deep branch history table (BHT) for dynamic branch prediction to produce four possible ...
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Feature Overview – BPU Execute Stage SRU Figure 3 shows a maximum depth of six stages using the floating-point unit. If branch prediction does not work well for a particular application, having a short pipeline is advantageous due to a ...
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VR Issue AltiVec Units VPU-E0 VPU-E1 VIU1 Finish Migrating from IBM 750GX to MPC7447A, Rev. 1.0 Freescale Semiconductor Fetch1 Fetch2 BPU Decode/Dispatch FPR Issue Queue Queue (FIQ) (VIQ) FPU-E0 VIU2-E0 VFPU-E0 FPU-E1 VIU2-E1 VFPU-E1 FPU-E2 VIU2-E2 VFPU-E2 FPU-E3 VIU2-E3 VFPU-E3 ...
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Feature Overview 2.3 L1 and L2 Cache Table 2 summarizes the differences if L1 and L2 cache configuration. Cache Description Size, configuration Memory Coherency Locking L1 Replacement policy Per page/block write configuration Size, configuration Memory Coherency L2 Locking Replacement policy ...
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Data Accesses EA[0–19] MMU X (32-Bit) EA[0–3] 0 Segment Registers 15 Upper 24-Bits of Virtual Address Page Table Search Logic (Optional) SDR1 SPR 25 Both the IBM 750GX and MPC7447A offer the same common features as seen below, • 128 ...
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Feature Overview The main difference is the fact that the MPC7447A can support 36-bit physical addressing by enabling HID0[XAEN], thus allowing the increased 64 Gbyte memory space. The extended block size of greater than 256 Mbyte is enabled by asserting ...
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MPC7447A. The monitor chip is also connected via the 60x or MPX bus to a bridge chip/system controller which then communicates with the monitor chip itself using I2C. This second connection allows ...
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Specific Features a more comparable format four 32-bit integer-based operations per instruction. These different levels of parallelism can be seen in Figure 7, 16x8 bit, 8x16 bit or 4x32 bit. Further explanation of AltiVec implementation and benefits would be ...
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CPU1 and already had a modified in its cache, then it would have changed its MEI status to Invalid and pushed the block into main memory causing CPU1 to wait for and then read the ...
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Programming Model The MPX bus mode’s support for data intervention and full data streaming for burst reads and writes is realized through the addition of two new signals—HIT and DRDY. The HIT signal is a point-to-point signal output from the ...
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USER MODEL—VEA Time Base Facility (For Reading) TBL TBR 268 TBU USER MODEL—UISA Count General-Purpose Register CTR SPR 9 XER XER SPR 1 Link Register LR SPR 8 Performance Monitor Registers (For Reading) 1 Performance Counters UPMC1 SPR 937 UPMC2 ...
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Programming Model USER MODEL—VEA Time Base Facility (For Reading) TBL TBR 268 TBU USER MODEL—UISA Count Register General-Purpose CTR SPR 9 XER XER SPR 1 Link Register LR SPR 8 Performance Monitor Registers Floating-Point 1 Performance Counters UPMC1 SPR 937 ...
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Differences in HID0 and HID1 Although both the IBM 750GX and MPC7447A have both of these registers defined in their implementation, the registers are optional to the standard and therefore differences in bit settings between devices do exist. summarizes ...
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Programming Model Table 4. IBM 750GX HID0 to MPC7447A Mapping Function Branch History Table enable No-op the data cache touch instructions 1. Not available in MPC7447A implementation. 2. Not required on MPC7447A due to processor-system handshake protocol system explained in ...
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Dual PLL Configuration The 750GX has dual PLL allowing the frequency to be selected from PLL0 or PLL1 where the transition is controlled through software. A change in clock frequency will take three cycles to complete. Due to the ...
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Programming Model To illustrate the simplicity of the DFS features: 1. The frequency is switched completely “on the fly”. 2. This change occurs in only one clock cycle requires zero any idle time or operations before or during ...
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Differences in L1 and L2 Cache Configuration Due to the differences in each programming model the L1 and L2 cache configuration and status bits are located in different registers for the MPC7447A from the IBM 750GX. There is no ...
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Programming Model Table 10 shows the mapping of the IBM 750GX’s L2CR to the MPC7447A. Table 10. IBM 750GX L2CR to MPC7447A Mapping Function L2 cache enable L2 double bit checkstop enable L2 data only L2 global invalidate L2 write ...
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Memory Management Registers Since the IBM 750GX does not have the ability to resolve page table entries in software it has no need for PTEHI, PTELO and TLBMISS registers known as SPR 981, 982 and 980 respectively. The TLBMISS ...
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Programming Model Function Disable counting while in user mode MMCR0[DU] Disable counting while MSR[PM] is set Disable counting while MSR[PM] is zero Enable performance monitor interrupt signaling Disable counting of PMCn when a performance monitor interrupt is signalled 64 bit ...
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Function PMC3 event selector, 32 events PMC4 event selector, 32 events PMC5 event selector, 32 events PMC6 event selector, 64 events 1. PMC5 and PMC6 not present in IBM 750GX. As mentioned previously the MPC7447A also has a MMCR2 register ...
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Hardware Considerations Signal Name Pin Number GBL W1 PLL_RNG W15, U14 RSRV Y4 TLBISYNC W11 Table 7 – PLL range configuration 5.1.2 MPC7447A Uncommon Pins Table 14 shows the signal name, pin number and a description of ...
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Pin Signal Name Number TEST[0:3] A12, B6, B10, E10 TEST[4] D10 VDD_SENSE G13, N12 Table 5 – PLL range configuration 5.2 60x Signal Differences One of the changes in terms of hardware between the IBM 750GX and ...
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Hardware Considerations Signal Description Data retry Reservation TLB invalidate synchronize 1. Use A[4-35] for 32 bit addressing, with A[0-3] pulled down if not in use bit mode AP[0] should be pulled up bit mode use ...
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THIS PAGE INTENTIONALLY LEFT BLANK Migrating from IBM 750GX to MPC7447A, Rev. 1.0 Freescale Semiconductor Hardware Considerations 29 ...
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Hardware Considerations THIS PAGE INTENTIONALLY LEFT BLANK Migrating from IBM 750GX to MPC7447A, Rev. 1.0 30 Freescale Semiconductor ...
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THIS PAGE INTENTIONALLY LEFT BLANK Migrating from IBM 750GX to MPC7447A, Rev. 1.0 Freescale Semiconductor Hardware Considerations 31 ...
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... Fax: 303-675-2150 LDCForFreescaleSemiconductor@ hibbertgroup.com AN2797 Rev. 1.0 10/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...