AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 18

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

Programming Model
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4.2
Although the IBM 750GX and MPC7447A are very similar, there are differences in power management
functionality. This section only mentions the differences. Features like Instruction Cache Throttling to slow the
instruction dispatch rate is the same in both implementations. Both implementations support the four states: Full
Power, Doze, Nap and Sleep.
From
the MPC7447A enters Doze mode when requested by the processor-system protocol. The processor can transition
to Doze mode from:
It can transition from Doze mode to:
Additionally, the MPC7447A has a Deep Sleep mode which can offer further power savings from Sleep mode by
turning off the PLL by setting PLL_CFG to 0xF and hence allowing the SYSCLK source to be disabled.
For further explanation on standard power management features between both implementations please refer to the
MPC7450 RISC Microprocessor Family User’s Manual.
4.2.1 PLL Configuration
HID1 primarily holds PLL configuration and other control bits in both the IBM 750GX and MPC7447A. However,
there are a couple of differences as shown below, due to the dual PLL in the 750GX, as compared to the Dynamic
Frequency Selection (DFS) in the MPC7447A (not featured in other current MPC7450 family devices). For this
reason, there is not a direct mapping between the two. The concept behind both schemes is to save power by reducing
the core clock rate when full rate is not required.
18
. Not implemented. For test only on the 750GX.
Not available in MPC7447A implementation.
Not required on MPC7447A due to processor-system handshake protocol system explained in Power Management.
Always enabled in MPC7447A implementation. The IBM 750GX supports 4 outstanding misses (3 data and 1 instruction or 4
Reserved. Used for IFEM in earlier processors but is also used for Extended BAT Block Size Enable.
Reserved. Defined as DCFA on earlier processors.
Must be enabled in multiprocessing systems. HID1[SYNCBE] enables address broadcast for sync and eieio instructions.
data) and the MPC7447A supports 5 outstanding data misses.
1. Full Power, if HID0[NAP] or HID0[SLEEP] is asserted and the core is idle.
2. Nap, if the system negates QACK to signal a snoop operation is outstanding.
1. Full Power, following one of many possible interrupts: external, SMI interrupt, SRESET, HRESET,
2. Nap, if the system asserts QACK with HID0[NAP] set.
or
3. Sleep, if system asserts QACK with HID0[SLEEP] set.
Table 4
machine check or decrementer interrupt.
Power Management
Function
Branch History Table enable
No-op the data cache touch instructions
above you should note that the there is no HID0[DOZE] bit for the MPC7447A and this is because
Table 4. IBM 750GX HID0 to MPC7447A Mapping
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
HID0[NOOPTI]
IBM 750GX
HID0[BHT]
MPC7447A
HID0[NOOPTI]
HID0[BHT]
Freescale Semiconductor