AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 22

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

Programming Model
Table 10
1. Not available in MPC7447A implementation.
2. IBM 750GX still has L2CR[LOCKLO] and L2CR[LOCKHI] for backwards compatibility when it could only lock the bottom two
4.4.1 MPC7450 Extended Capabilities
The MPC7447A also offers the choice of the first or second replacement algorithm, L2CR[L2REP], and an L2
hardware flush feature, L2CR[L2HWF], which the 750GX does not.
An L2 feature supported on the MPC7447A family but not the 750GX is L2 prefetching. This can offer an
improvement in performance by loading the second block of a cache line after a cache miss on the line. The idea
being that the second block maybe required in the near future even if it is not required right now. The MPC7447A
family takes advantage of this concept, known as spatial locality, using up to 3 hardware prefetch engines.
The L2 prefetching feature can be enabled by setting the L2 prefetch enable bit in memory configuration subsystem
register, MSSCR0[PFE], providing the L2 cache is enabled and not configured as data or instruction only.
4.4.2 L1 and L2 Cache Locking
The MPC7447A contains a Load/Store Control Register which configures L1 data cache locking by way. The
LDSTCR is not present in the IBM 750GX because it is not supported. It can be configured on the MPC7447A using
the 8 bits in LDSTCR[DCWL], indicating which way(s) to lock.
Similarly ICTRL is also not present on the IBM 750GX since its ICTRL[ICWL]is used to lock the L1 instruction
cache by way which is not supported in the IBM 750GX.
The IBM 750GX has the ability to lock L2 cache by way using L2CR[LOCK] bits and L2CR[DO] or L2CR[IO] to
set the L2 as data or instruction. The MPC7447A does not support locking by way but the whole cache can be locked
by setting both L2CR[DO] AND L2CR[IO].
22
ways or top two ways.
Function
L2 cache enable
L2 double bit checkstop enable
L2 data only
L2 global invalidate
L2 write through
L2 test support
L2 cache way locking
Snoop hit in locked line checkstop
enable
Snoop hit in locked line error
L2 instruction only
L2 global invalidate progress bit
shows the mapping of the IBM 750GX’s L2CR to the MPC7447A.
Table 10. IBM 750GX L2CR to MPC7447A Mapping
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
IBM 750GX
L2CR[L2E]
L2CR[CE]
L2CR[DO]
L2CR[GI]
L2CR[WT]
L2CR[TS]
L2CR[LOCK]
L2CR[SHEE]
L2CR[SHEER]
L2CR[IO]
L2CR[IP]
2
MPC7447A
L2CR[L2E]
N/A
L2CR[DO]
L2CR[L2I]
N/A
N/A
L2CR[D0] and L2CR[IO]
N/A
N/A
L2CR[IO]
N/A
1
1
1
1
1
1
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