AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 12

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

7447A Specific Features
a more comparable format four 32-bit integer-based operations per instruction. These different levels of parallelism
can be seen in
Further explanation of AltiVec implementation and benefits would be out of the scope of this document and
therefore please refer to MPC7450 RISC Microprocessor Family User’s Manual for additional information.
3.2
Another important difference is the difference between the MEI cache coherency features on the 750GX and the
enhanced MESI capability of the 7447A. These protocols are used as a coherency mechanism in SMP (Symmetric
Multi-Processing) configurations to indicate the relationship between 32-byte blocks stored in cache and their
corresponding blocks in main memory. In an SMP system, some or all of the main memory is shared. Therefore, it
is important to find the most efficient method of maintaining coherency across the caches and memory of the CPUs.
MEI refers to the cache coherency states available in the 750GX:
An example of an MEI protocol operation is a dual processor SMP system using 750GX processors. The processors
and CPU1 and CPU2 operate on a shared area of memory. If CPU1 loads a cache line from this area of main memory
it is marked as Exclusive with the assumption that the cache has been flushed on both CPUs. If, however, CPU2
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Modified (M) This block is modified with respect to main memory
Exclusive (E) This block is valid and only present in this CPU’s cache
Invalid (I) This block is invalid with respect to main memory
Comparing MESI and MEI
Figure
7, 16x8 bit, 8x16 bit or 4x32 bit.
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
Figure 7. AltiVec Degrees of Parallelism
Freescale Semiconductor