AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 23

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

4.5
Since the IBM 750GX does not have the ability to resolve page table entries in software it has no need for PTEHI,
PTELO and TLBMISS registers known as SPR 981, 982 and 980 respectively.
The TLBMISS register is automatically loaded when software searching is enabled (HID0[STEN] = 1) and a TLB
miss exception occurs. Its contents are used by the TLB miss exception handlers (the software table search routines)
to start the search process.
The PTEHI and PTELO registers are used by the tlbld and tlbli instructions to create a TLB entry. When software
table searching is enabled, and a TLB miss exception occurs, the bits of the page table entry (PTE) for this access
are located by software and saved in the PTE registers.
A full explanation of software page table searching can be found in the MPC7450 RISC Microprocessor Family
User’s Manual.
4.6
Although it is optional, both implementations support the Performance Monitor features. This gives the user
software the ability to monitor and count specific events including processor clocks, L1 and L2 cache misses, types
of instructions dispatched and branch prediction statistics, among others. The count of these events can be used to
trigger an exception.
In the MPC7447A the Performance Monitor has three key objectives:
The MPC7447A contains two additional Performance Counters, PMC5 and PMC6, a Breakpoint Address Mask
Register, BAMR, and an extra Monitor Control Register, MMCR2. This section looks at any differences in the
common registers and the purpose of the extra MPC7447A registers. The MPC7447A offers the extra registers to
monitor more events including AltiVec based events which the IBM 750GX obviously does not have to support. Full
listings of PMC events available in each implementation can be found in IBM PowerPC 750GX RISC
Microprocessor User Manual and MPC7450 RISC Microprocessor Family’s User Manual.
Each implementation provides read registers in user mode for PMC and MMCR registers with the prefix U, for
example UPMC1 or UMMCR1.
4.6.1 Monitor Mode Control Registers
The mapping between the MMCR0 and MMCR1 is very similar but not identical.
mapping for the IBM 750GX MMCR0 and MMCR1 respectively.
Freescale Semiconductor
•
•
•
Function
Disable counting unconditionally
Disable counting while in supervisor
mode
To increase system performance with efficient software, especially in a multiprocessing system—Memory
hierarchy behavior can be monitored and studied in order to develop algorithms that schedule tasks (and
perhaps partition them) and that structure and distribute data optimally.
To characterize processors—Some environments may not be easily characterized by a benchmark or trace.
To help system developers bring up and debug their systems.
Memory Management Registers
Performance Monitor
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
Table 11. IBM 750GX MMCR0 to MPC7447A
IBM 750GX
MMCR0[DIS]
MMCR0[DP]
MPC7447A
MMCR0[FC]
MMCR0[FCS]
Table 11
and
Table 12
Programming Model
shows this
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