AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 6

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

Feature Overview
Figure 3
for a particular application, having a short pipeline is advantageous due to a fairly small pipeline flushing penalty.
However, branch prediction and modern compilers can, more often than not, prevent frequent pipeline flushes. As
a result, the completion rate of two instruction retirements per clock becomes more of a performance bottleneck. It
is also worth noting that the IBM 750GX will not be able to sustain clock rates of much greater than 1.1GHz without
increasing the depth of the pipeline.
With a minimum depth of seven stages, the MPC7447A pipeline, shown in
additional hardware resources by dispatching three instructions per cycle to its execution units as well as the ability
to retire three instructions per cycle. Due to the higher maximum frequency of the 7447A (up to 1.5GHz) the extra
pipeline depth is required to make efficient use of faster running pipeline stage hardware, reducing the latency of
certain instructions, such as many floating point and complex integer instructions. Compilers can take advantage of
the extended pipeline to ensure that the target maximum of 16 instructions in flight at any one time is achieved as
closely as possible.
6
–
shows a maximum depth of six stages using the floating-point unit. If branch prediction does not work well
Execute Stage
BPU
SRU
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
Figure 3. IBM750GX Pipeline Diagram
FPU1
FPU2
FPU3
Complete (Write-Back)
Decode/Dispatch
Fetch
IU1
IU2
Figure
Maximum 4-instruction
fetch per clock cycle
Maximum 4-instruction
dispatch per clock cycle
(Includes one branch
instruction)
Maximum 2-instruction
completion per clock cycle
4, boasts efficient use of its
LSU1
LSU2
Freescale Semiconductor