AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 21

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

4.4
Due to the differences in each programming model the L1 and L2 cache configuration and status bits are located in
different registers for the MPC7447A from the IBM 750GX.
There is no HID2 register in the MPC7447A so the following table shows which register bits give the same
functionality in the MPC7447A. HID2 is used for L1 and L2 cache parity error settings and status in the IBM
750GX. As you can see from
bits in question are reserved, as well MSSSR and Instruction Cache and Interrupt Control Register, ICTRL, which
the IBM 750GX does not have.
1.
2.
3.
Freescale Semiconductor
Not available in MPC7447A implementation.
Enables tag AND data parity.
When the EICP bit is set, the parity of any instructions fetched from the L1 instruction cache
are checked. Any errors found are reported as instruction cache parity errors in SRR1. If EICE
is also set, these instruction cache errors cause a machine check or checkstop. If either EICP
or EICE is cleared, instruction cache parity is ignored.
Note that when parity checking and error reporting are both enabled, errors are reported even
on speculative fetches that are never actually executed. Correct instruction cache parity is
always loaded into the L1 instruction cache regardless of whether checking is enabled or not.
Function
Disable store under miss
processing. (Permitted outstanding
stores changes from two to one)
Force instruction-cache bad parity
Force instruction-tag bad parity
Force data-cache bad parity
Force data-tag bad parity
Force L2-tag bad parity
L1 instruction-cache/instruction-tag
parity error status/mask
L1 data-cache/data-tag parity error
status/mask
L2 tag parity error status/mask
Enable L1
instruction-cache/instruction-tag
parity checking
Enable L1 data-cache/data-tag
parity checking
Enable L2 tag parity checking
Differences in L1 and L2 Cache Configuration
Table
Table 9. IBM 750GX HID2 to MPC7447A Mapping
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
9, these functions are spread across SSR1 which the IBM 750GX has but the
IBM 750GX
HID2[STMUMD]
HID2[FICBP]
HID2[FITBP]
HID2[FDCBP]
HID2[FDTBP]
HID2[FL2TBP]
HID2[ICPS]
HID2[DCPS]
HID2[L2PS]
HID2[ICPE]
HID2[DCPE]
HID2[L2PE]
MPC7447A
N/A
N/A
N/A
N/A
N/A
N/A
SRR1[1]
SRR1[2]
MSSSR[L2TAG] – Tag error
(MSSSR[L2DAT]) – Data error
ICTRL[EICE]
(ICTRL[EICP])
ICTRL[EDEC]
L2CR[L2PE]
1
1
1
1
1
1
3
2
Programming Model
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