AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 13

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

snooped the read request from CPU1 and already had a modified in its cache, then it would have changed its MEI
status to Invalid and pushed the block into main memory causing CPU1 to wait for and then read the latest version
of the data. Then, if CPU2 tries to read the data again, it must read it from main memory; and to make the situation
worse, CPU1 may have since modified the data in its cache. If CPU1 did modify the data then CPU2 would have to
wait for CPU1 to write its data back to memory for the CPU2 to access.
The extra bandwidth used and time wasted in waiting for each CPU to write its cache block back to memory for the
other CPU to access is a very inefficient use of the bus. To help combat this problem the MPC7447A supports the
MPX bus which extends the 60x functionality with some efficiency improvements as discussed in the next section.
The main method used to improve performance on MPC7447A was to incorporate the MESI protocol which
includes the new shared state:
The addition of this state reduces the wasted time and bandwidth associated with MEI coherency and requires an
additional 60x/MPX signal called SHD. If we look at the previous example it is easy to see the benefits of the MESI
over MEI. If CPU1 tried to read a block of main memory to its cache, CPU2 would snoop the transaction as before
but this time assert the SHD signal to tell CPU1 that it also has a cached copy of this block. CPU1 would load the
block into it’s cache with shared status and CPU2 would change it’s cache entry to shared from exclusive, allowing
both CPUs to access the data quickly from cache provided that the data is only.
3.3
The MPX bus protocol is based on the 60x bus protocol. It also includes several additional features that allow it to
provide higher memory bandwidth than the 60x bus and more efficient utilization of the system bus in a
multiprocessing environment.
Memory accesses that use the MPX bus protocol are divided into address and data tenures. Each tenure has three
phases: bus arbitration, transfer, and termination. The MPX bus protocol also supports address-only transactions.
Note that address and data tenures can overlap. One of the key differences to the 60x bus is that the MPX does not
require an idle cycle between tenures. To illustrate the importance of this difference, consider the following example:
Also, taking into account the higher bus speeds of 167MHz available on the 7447A, this figure is scaled accordingly
to give significant increase to 1336MB/s, which compares favorably to the 750GX 1280MB/s maximum with its
200MHz 60x bus.
The address and data tenures in the MPX bus protocol are distinct from one another and each tenure consists of three
phases—arbitration, transfer, and termination. The separation of the address and data tenures allows advanced bus
techniques—such as split-bus transactions, enveloped transactions, and pipelining—to be implemented at the
system level in multiprocessor systems.
Freescale Semiconductor
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Shared (S) - This block exists in multiple caches and is consistent with main memory, for example, it is read
only
100Mhz 60x bus:
— Transfer rate = (32 bytes / 5 clock cycles) * 100MHz = 640MB/s
100Mhz MPX bus:
— Transfer rate = (32 bytes / 4 clock cycles) * 100MHz = 800MB/s
MPX Mode
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
7447A Specific Features
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