RTL8181 ETC, RTL8181 Datasheet - Page 21

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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The read access timing of flash memory:
F_CE0#
8. Ethernet Controller
There are two 10/100M Ethernet MAC embedded in RTL8181. The Ethernet device has bus master capability, which will
move packets between SDRAM and Ethernet controller through DMA mechanism. Thus, it could offload the CPU loading and
get better performance. Besides, it also supports full-duplex operation, making possible 200Mbps bandwidth at no additional
cost.
Ethernet 0 Register Set (LAN PORT)
Virtual Address Size (byte) Name
0xBD20_0000
0xBD20_0004
0xBD20_000C
0xBD20_0014
0xBD20_0018
0xBD20_0020
0xBD20_0024
0xBD20_0028
0xBD20_002C
0xBD20_0030
0xBD20_0034
0xBD20_0038
0xBD20_003C
0xBD20_0040
0xBD20_0080
0xBD20_0084
0xBD20_0088
Ethernet 1 Register Set (WAN PORT)
Virtual Address Size (byte) Name
0xBD30_0000
0xBD30_0004
0xBD30_000C
CONFIDENTIAL
A[20..0]
D[n..0]
WE#
OE#
4
6
8
4
4
2
2
4
4
4
4
4
4
16
3
2
2
4
6
8
ETH0_CNR1
ETH0_ID
ETH0_MAR
ETH0_TSAD
ETH0_RSAD
ETH0_IMR
ETH0_ISR
ETH0_TMF0
ETH0_TMF1
ETH0_TMF2
ETH0_TMF3
ETH0_MII
ETH0_CNR2
ETH0_UAR
ETH0_MPC
ETH0_TXCOL Transmit collision counter. This
ETH0_RXER
ETH1_CNR1
ETH1_ID
ETH1_MAR
Description
Control register 1
NIC ID
Multicast register
Transmit Starting Logic Address of
Descriptor
Receive Starting Logic Address of
Descriptor
Ethernet0 Interrupt Mask Register
Ethernet0 Interrupt Status Register
Type match filter 0 register
Type match filter 1 register
Type match filter 2 register
Type match filter 3 register
MII access register
NIC control register 2
Unicast address filter register
Indicates the number of packets
discarded due to rx FIFO overflow.
It is a 24-bit counter. It is cleared to
zero by read command.
16-bit counter increments by 1 for
every collision event. It rolls over
when becomes full. It is cleared to
zero by read command.
Receive error count. This 16-bit
counter increments by 1 for each
valid packet received . It is cleared
to zero by read command.
Description
Control register 1
NIC ID
Multicast register
21
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Access
R/W
R/W
R/W
RTL8181
v1.0