RTL8181 ETC, RTL8181 Datasheet - Page 24

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

www.DataSheet4U.com
3-0
Note: Bit UAEN is only existed in ETH0_CNR2 register.
Unicast Address Filter Register (ETH0_UAR)
Bit
127-0
Interrupt Mask Register (ETH0_IMR, ETH1_IMR)
Bit
9
8
7
6
5
4
3
2
1
0
Interrupt Status Register (ETH0_ISR, ETH1_ISR)
Bit
9
8
7
6
5
4
3
CONFIDENTIAL
TXRR[3:0]
Bit Name
UARTBL
Bit Name
LINKCHGIE
RERIE
TERIE
ROKIE
TOKIE
RFOVWIE
RDUIE
Reserved
TDUIE
SWIE
Bit Name
LINKCHGIP
RERIP
TERIP
ROKIP
TOKIP
RFOVWIP
RDUIP
000: 9.6+20*0.1us/ 960+20*10ns
001: 9.6+24*0.1us/ 960+24*10ns
010: 9.6+48*0.1us/ 960+48*10ns
Tx Retry Count: These are used to specify
additional transmission retries in multiple of
16(IEEE 802.3 CSMA/CD retry count). If the
TXRR is set to 0, the transmitter will re-transmit
16 times before aborting due to excessive
collisions. If the TXRR is set to a value greater
than 0, the transmitter will re-transmit a number of
times equals to the following formula before
aborting:
The TER bit in the ISR register or transmit
descriptor will be set when the transmission fails
and reaches to this specified retry co unt.
Description
Unicast address hash table. If the ‘n’ bit value is
set ‘1’, it implies the receiving frames which hash
value with ‘n’ will be indicated.
Description
Link status changed interrupt enable
Rx error interrupt enable
Tx error interrupt enable
ROK interrupt enable. A descriptor reception is
completed successfully.
TOK interrupt enable. A descriptor transmission is
completed successfully.
Rx FIFO overflow interrupt enable
Rx descriptor unavailable interrupt enable. Set
when the Rx Descriptors have been exhausted.
Tx descriptor unavailable interrupt enable
Software interrupt enable
Description
Link status changed interrupt pending flag. Write
“1” to clear the interrupt.
Rx error interrupt pending flag. Write “1” to clear
the interrupt.
Tx error interrupt enable flag. Write “1” to clear
the interrupt.
ROK interrupt pending. A descriptor reception is
completed successfully. Write “1” to clear the
interrupt.
TOK interrupt pending. A descriptor transmission
is completed successfully. Write “1” to clear the
interrupt.
Rx FIFO overflow interrupt pending Write “1” to
clear the interrupt..
Rx descriptor unavailable interrupt pending. Set
when the Rx Descriptors have been exhausted.
Write “1” to clear the interrupt and it also trigger
24
Total retries = 16 + (TXRR * 16)
R/W 0
R/W InitVal
R/W 0
R/W InitVal
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W InitVal
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
RTL8181
v1.0