RTL8181 ETC, RTL8181 Datasheet - Page 4

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RTL8181

Manufacturer Part Number
RTL8181
Description
Wireless LAN Access Point/Gateway Controller
Manufacturer
ETC
Datasheet

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1. Overview
RTL8181 is a highly integrated SoC, embedded with a high-performance 32-bit RISC microcontroller, Ethernet and WLAN
controller. It is a cost-effective and high- performance solution for the system of wireless LAN Access Point, wireless SOHO
router, wireless Internet gateway, etc.
System block diagram:
The embedded processor of RTL8181 is Lexra LX5280 32bit RISC CPU, with 8K separate instruction and data caches. A
protection unit (MMU) allows the memory be segmented and protected, and this unit is required in the modern operation
system (e.g., Linux).
The processor pipeline is a dual - issues and 6 stage architecture. The dual - issue CPU fetches two instructions per cycle, and
which could allow two instructions are executed concurrently in two pipes via some instructions. Thus, its performance will
achieve up to 30% improvement over uni-scalar architecture.
Besides, it includes two fast Ethernet MACs, one could be used for LAN interface and the other one could connect to WAN
port. An IEEE 802.11b WLAN MAC+Baseband processor is embedded as well. By this build- in wireless controller, it could
save a lot of costs and space comparing with the system designed with an external 802.11b adapter.
The RTL8181 also integrates with memory controller, which allows customers use external SDRAM and Flash memory in
glueless.
A PCI interface is supported as well, which enables customers to plug in a PCI device seamlessly. For example, an IEEE
802.11a device could be connected through this PCI interface to provide the WLAN dual mode service.
Features
Core Processor
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WLAN Controller
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CONFIDENTIAL
Watchdog
EJTAG
UART
GPIO
LX5280 32-bit RISC architecture.
Superscalar architecture, containing 2 execution pipelines with better performance
Embedded with 8K I-Cache, 8K D-Cache and 4K D-RAM.
MMU supported
Up to 200MHZ operating frequency
Integrated IEEE 802.11b complied MAC and DSSS Baseband processor
Support Tx data rate in 11M, 5.5M, 2M and 1M
Support long and short preamble
Support antenna diversity and AGC.
Embedded with encryption/decryption engine for 64 bits and 1 28 bits WEP
Timer
Flash
Memory controller
Microprocessor
Cache buffer
MMU
SDRAM
802.11b MAC/BB
Ethernet MAC0
Ethernet MAC1
PCI Bridge
4
MII
MII
RF transceiver
Ethernet PHY
Ethernet PHY
PCI device
PCI device
LAN
WAN
RTL8181
v1.0

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