RTL8181 ETC, RTL8181 Datasheet - Page 25

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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2
1
0
MII Access Register (ETH0_MII, ETH1_MII)
Bit
31-22
21
20-16
15
14
13
12
11
10
9
8
7-5
4
CONFIDENTIAL
Reserved
TDUIP
SWIP
Bit Name
-
MMIMODE
PHYAD[4:0]
LinkCtrl
DplxCtrl
SpdCtrl
FlCtrl
LinkSt
DuplexSt
SpeedSt
FlCtrlSt
-
DisNway
NIC to send PAUSE 0x0000 packet.
Tx descriptor unavailable interrupt pending flag.
Write “1” to clear the interrupt.
Software interrupt pending flag. Write “1” to clear
the interrupt.
Description
Reserved
Mode of MII management interface. (Realtek
internal use only to test 3-port switch)
0 = auto mode. The NIC controls MDC and MDIO
pins. Setting this bit will trigger an
auto- negotiation if DisNway bit is cleared.
1 = manual mode. The software controls MDC and
MDIO pins.
PHY address.
Link control.
0: force link down.
1: force link up.
Duplex control. When DuplexCtrl bit is cleared,
this bit is read only. The NIC will poll its local
PHY regularly. This bit will reflect the result of
auto- negotiation from its local PHY. If FDuplex is
set, this bit is writable. The software may program
the bit and force the MII operates in full-duplex or
half-duplex mode.
0: Force half-duplex mode.
1: Force full-duplex mode.
Speed control.
0: 10Mbps
1: 100Mbps.
Flow control.
0:disable flow control.
1: enable flow control.
Link status. This bit reflects the link status from its
local PHY.
0: link down
1: link up
Duplex status. This bit reflects the duplex status
from its local PHY.
0: half duplex
Speed status. This bit reflects the link speed from
its local PHY.
0: 10Mbps
1: 100Mbps
Flow control status
0: flow control disabled
1: flow control enabled.
Reserved
Disable N-way
0: auto- negotiation mode.The local PHY will
advertise its capability per the settings of
DplxCtrl, SpdCtrl, and FlCtrl bits.
1: forced mode (disable N-way). The software
may force MII operating mode by writing the
corresponding value to the DplxCtrl, LinkCtrl,
SpdCtrl,FlCtrl bits.
25
R/W 0
R/W 0
R/W InitVal
R/W 0
R/W 0x01
R/W 0
R/W 1
R/W
R/W
R
R
R
R
R/W 0
1
0
0
0
0
0
RTL8181
v1.0