RTL8181 ETC, RTL8181 Datasheet - Page 35

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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Bit
10-9
8
7-0
11. GPIO Control
RTL8181 provides two sets of GPIO pins – PortA and PortB . PortA has 16 pins and PortB has 16 pins. Every GPIO pin can
be configured as input or output pins via register PA(B)DIR. Register PA(B)DATA could be used to control the signals (high
or low) of GPIO pins. Because the GPIO pins might be shared with some peripheral pins, the PA(B)CNR can control the
attribute of the shared pins. Besides, PortB GPIO sets can be used to generate interrupt via PBIMR , and the interrupt status is
shown in PBISR.
GPIO Register Set
Virtual address Size (byte) Name
0xBD01_0040
0xBD01_0044
0xBD01_0048
0xBD01_004C
Port A,B Direction Register (PADIR , PBDIR)
Bit
31-16
15-0
Port A,B DATA Register (PADATA, PBDATA)
Bit
31-16
15-0
Port B Interrupt Mask Register (PBIMR)
Bit
1-0
3-2
CONFIDENTIAL
Bit Name
OVSEL[1:0]
WDTCLR
WDTE[7:0]
Bit Name
DRCA[15:0]
DRCB[15:0]
Bit Name
DATAA[15:0] Pin data of Port A
DATAB[15:0] Pin data of Port B
Bit Name
PB0IM[1:0] PortB.0 interrupt mode
PB1IM[1:0] PortB.1 interrupt mode
4
4
4
4
Description
00 = disable interrupt
01 = enable falling edge interrupt
10 = enable rising edge interrupt
11 = enable both falling or rising edge interrupt
00 = disable interrupt
01 = enable falling edge interrupt
Description
Pin direction configuration of Port A
0 = configured as input pin
1 = configured as output pin
Pin direction configuration of Port B
0 = configured as input pin
1 = configured as output pin
Description
Description
Overflow select. These bits specify the overflow
condition when the watchdog timer counts to the
value.
00 = 2
01 = 2
10 = 2
11 = 2
Watchdog clear. Write a 1 to clear the watchdog
counter. It is auto cleared after the write.
Watchdog enable. When these bits are set to 0xA5,
the watchdog timer stops. Other value can enable
the watchdog timer and cause a system reset when
an overflow signal occurs.
PABDIR Port A/B direction register
PABDAT
A
PBIMR
PBISR
13
14
15
16
Description
Port A/B data register
Port B interrupt mask register
Port B interrupt register
35
R/W
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R
InitVal
00
00
InitVal
00
00
InitVal
00
00
InitVal
00
0
0xA5
RTL8181
v1.0