SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 135

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bit 1
bit 0
bit 7
bit 5
bit 4
SPC8106
03 Power Save Register RW
Windows
Power Save
Mode
411-1.0
n/a
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
MEMEN
When this option is selected, then the MEMEN input pin is used as the clock source in Power Save
Mode 4 and Suspend.
Self Refresh
This option may only be used when the DRAMs installed are capable of self-refresh. When this
option is selected, during Power Save Mode 4 and Suspend mode, the DRAM control lines are
driven in such a manner to cause the DRAM to enter self-refresh mode. When not in self refresh
mode, then CAS-before-RAS refresh cycles are used during Power Save Mode 4 or Suspend
mode. Note that regardless of the setting of these bits, CAS-before-RAS refresh cycles are used
during active mode and Power Save Modes 1, 2 and 5.
PDCLK
When this option is selected, the PDCLK input pin is used as the clock source in Power Save Mode
4 and Suspend. For normal refresh rate DRAM (256 cycle/4 ms), this input should be a 64 kHz
clock source. If a 64 kHz clock source is attached to this input, for lowest possible DRAM power
consumption this input clock should have as short as possible high duration (but > min RAS pulse
width). It is possible to use a 32 kHz 50% duty cycle clock for PDCLK - see “Power Save Mode
Control Pins” on page 21 for details.
LCD Signal PS Mode State
The LCD Signal PS Mode State bit controls the states of the LCD interface signals (UD[3:0],
LD[3:0], XSCL, XSCL2, LP, YD, WF) when the chip goes into a power save mode. When this bit = 0,
the LCD signals are put into a high-impedance state when a power save mode is entered. When
this bit = 1, then when the chip is in a power save mode, the LCD interface signals will be forced
low. On RESET, this bit is set to 1.
32/4 ms Refresh Select
The 32/4 ms Refresh Select bit is used to select 256 cycle/4 ms or 256 cycle/32 ms DRAM refresh
timing in all modes of operation. When this bit is 0, then 4 ms refresh timing is generated. When
this bit is 1, then 32 ms refresh timing is generated. In active mode and Power Save Modes 1, 2
and 5, this 4 or 32 ms refresh timing is generated from the selected CLKI source (28 MHz for LCD
modes, 25 MHz or 28 MHz for CRT modes as selected by Clock Select bits in Misc Output Register
3C2h). For Power Save Mode 4 and Suspend, this 4 or 32 ms refresh timing is generated from the
active CLKI, from MEMEN input, or the PDCLK input, as selected by AUX[02] bits 3,2.
Windows Power Save Mode
Setting the Windows Power Save Mode bit to 1 bypasses the Graphics Blink and Pel Panning logic
to reduce power consumption. This bit should be set for mode 12h operation from within a Win-
dows driver only.
Clock Slow Down
The Clock Slow Down bit is used to provide additional power savings in some LCD modes. When
this bit is set to 1, then the active internal clock rate is reduced by 20%. When this bit is set to 0,
then the internal clock rate equals the input clock rate. This bit is intended for use in Power Save
Mode 5. If CRT mode is enabled (AUX[0B] bit 1 = 1), then this bit is ignored and has no effect.
Oscillator Disable
The Oscillator Disable bit is used to control the operation of the internal clock oscillators connected
to the external 2-terminal crystals. When this bit = 0 the oscillators are enabled. When this bit 1 the
oscillators are disabled and the corresponding CLKI inputs are masked off.
Clock Slow
Down
Oscillator
Disable
X12-SP-001-07
Aux Reg
Only
Decode
Power Save
Mode
Select Bit 2
Hardware Functional Specification
Power Save
Mode
Select Bit 1
Power Save
Mode
Select Bit 0
SP1-93