SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 67

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Pin Mapping for Various DRAM Configurations
Non-italicized pin names are the default configuration and correspond to the names on the pinout
diagram.
Address Mapping for 256Kx16 DRAMs
Two addressing configurations of 256Kx16 DRAMs are supported by the SPC8106:
The SPC8106 is designed to accommodate both types of 256Kx16 DRAMs directly without any
special configuration options required. The full addressing space is available for either memory
configuration. The only difference is that in the installation of the 10x8 type of DRAM, an extra
row/column address output pin of the SPC8106 (MA[9]) must be connected to the DRAM. For the
9x9 DRAM, only 9 row/column address pins exist, so MA[9] from the SPC8106 is left uncon-
nected.
The following tables summarize the mapping of the SPC8106’s internal memory address bits
a[17:0] to the multiplexed row/column address outputs MA[9:0] for the two types of DRAM.
SPC8106
1. For the 10x8 type DRAMs:
2. For the 9x9 type DRAMs:
1. the address pin mapping for both types of DRAM are actually the same.
2. for the standard 256K byte VGA address space, a[17] is normally = 0, and for the upper 256K
bytes, a[17] = 1.
3. the 10x8 type DRAM does not use the 9th column bit MA[8] - it is ignored.
4. a[17] is output on the 9th column bit MA[8], so the same physical addressing scheme works
for both 10x8 and 9x9 type DRAMs. In the case of the 10x8 type DRAM, this 9th column address
bit is not used by the DRAM ( italicized in the above table).
5. the 9x9 configuration does not have a 10th row/column address bit.
411-1.0
1024 x 256 x 16
512 x 512 x 16
Table 0-13 DRAM Configuration Pin Mapping
column addr
column addr
Pin #
60
61
62
row addr
row addr
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Table 0-14 10x8 DRAM Address Mapping
Table 0-15 9x9 DRAM Address Mapping
MD[6] = 1 MD[6] = 0
UCAS#
WE#
LCAS#
10 row address bits
9 row address bits
CAS#
UWE#
LWE#
MA[9]
MA[9]
a[17]
n/c
n/c
-
x 8 column address bits
x 9 column address bits
X12-SP-001-07
MA[8]
MA[8]
a[17]
a[16]
a[17]
a[16]
MA[7:0]
MA[7:0]
a[15:8]
a[15:8]
a[7:0]
a[7:0]
Hardware Functional Specification
SP1-25