SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 73

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

This table refers to standard ISA CPU bus timing. When configuration input MD[5] = 1 on the fall-
ing edge of RESET, refer to “Bus Cycle Timing - 16-bit Memory (Modified Address Timing)” on
page 34 for modified address timing.
Parameter t13 maximum only occurs when a refresh cycle is pending during fast dot, text modes.
Typical values are much shorter.
SPC8106
Symbol
t12a
t12b
t10
t11
t13
t14
t15
411-1.0
t1
t2
t3
t4
t5
t6
t7
t8
t9
ALE pulse width
LA[23:17] valid setup to ALE negated
LA[23:17] valid hold from ALE negated
LA[23:17] valid setup to MEMR#, MEMW# asserted
A[16:0], BHE#, MEMEN valid setup to MEMR#,
MEMW# asserted
A[16:0], BHE#, MEMEN hold from MEMR#, MEMW#
negated
D[15:0] (write) delay from MEMW# asserted
D[15:0] (write) hold from MEMW# negated
MEMCS16# asserted from valid LA[23:17]
MEMCS16# hold from LA[23:17] invalid
READY negated from MEMR#, MEMW# asserted
READY negated pulse width (dual panel)
READY negated pulse width (single panel)
D[15:0] (read) valid from READY released
D[15:0] (read) hold from MEMR# negated
MEMR# negated to D[15:0] high-impedance
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Table 0-21 CPU Bus Cycle Timing - 16-bit Memory
Parameter
X12-SP-001-07
Min
30
20
10
10
10
10
10
6
6
Hardware Functional Specification
Typ
138Ts +24
107Ts +24
3Ts-10
Max
30
50
40
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP1-31