SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 75

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

This table refers to standard ISA CPU bus timing. When configuration input MD[5] = 1 on the fall-
ing edge of RESET, refer to “CPU Bus Cycle Timing - 16-bit I/O (Modified Address Timing)” on
page 35 for modified address timing.
SPC8106
Symbol
t4a
t4b
t4c
t4d
t10
t11
t12
411-1.0
t1
t2
t3
t5
t6
t7
t8
t9
A[15:0], BHE# valid setup to IOR#, IOW# asserted
A[15:0], BHE# valid hold from IOR#, IOW# negated
IOEN# setup to IOR#, IOW# asserted
IOW# pulse width (16 bit access)
IOR# pulse width (16 bit access)
IOW# pulse width (8 bit access)
IOR# pulse width (8 bit access)
valid D[15:0] (write) setup to IOW# asserted
valid D[15:0] (write) hold from IOW# negated
IOCS16# asserted from A[15:0] valid
IOCS16# hold from A[15:0] invalid
D[15:0] (read) driven delay from IOR# asserted
valid D[15:0] (read) from IOR# asserted
D[15:0] (read) hold from IOR# negated
IOR# negated to D[15:0] high-impedance
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Table 0-22
Parameter
CPU Bus Cycle Timing - 16-bit I/O
X12-SP-001-07
Min
120
180
200
160
10
10
50
10
10
12
5
6
Hardware Functional Specification
Typ
Max
150
30
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP1-33