SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 166

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

11.0 PIN TEST MODE
To allow board level connectivity testing of the SPC8106, the pins have been defined such that all
output pins except IRQ are actually bidirectional pins whose outputs are placed in tri-state when
the SPC8106 is placed in pin test mode.
Pin test mode is enabled when any three of MEMR#, MEMW#, IOR# and IOW# are simulta-
neously low. When in scan mode the SPC8106 operates as shown in the following figure, with all
the SPC8106 pins, except CLKI1, CLKI2, CLKO1, CLKO2 and IRQ, connected as inputs to a
NAND-tree. The input order of the NAND-tree is given in the table on the following page. Note that
the MEMR#, MEMW#, IOR# and IOW# inputs to the NAND tree are inverted allowing the signals
to remain low, enabling scan mode, and still remain part of the NAND-tree.
To avoid race conditions all four of the MEMR#, MEMW#, IOR# and IOW# signals should be low
before setting any of the MEMR#, MEMW#, IOR# and IOW# signals high during scan.
Hardware Functional Specification
SP1-124
1
2
3
4
5
6
7
8
9
10
11
12
Position
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
MS2
MS1
MS0
MEMW#
IOR#
IOW#
MEMR#
BHE#
MEMEN
IOEN
ALE
RESET
All Other Signals
Signal
Table 0-68 Pin Test Input Order in NAND Tree
MEMW
MEMR
PCLK
IOW
MS0
MS1
MS2
IOR
Figure 41 : SPC8106 Pin Test Configuration
41
42
43
44
45
46
47
48
49
50
51
52
Position
UD1
UD0
LD3
LD2
LD1
LD0
MA9
MA8
MA7
MA6
MA5
MA4
Enable
Circuit
CLKI1
X12-SP-001-07
Signal
CLKO1
81
82
83
84
85
86
87
88
89
90
91
92
CLKI2
Position
CLKO2
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
Signal
IRQ
411-1.0
SPC8106