SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 78

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

7.6
Hardware Functional Specification
Symbol
SP1-36
t10
t11
t1
t2
t3
t4
t5
t6
t7
t8
t9
Note: DRAM access time is guaranteed to be 80 nsec minimum.
DRAM Read Cycle Timing - Non-Page Mode
DRAM outputs
SPC8106 outputs
Figure 9 : DRAM Read Cycle Timing - Non-Page
MA[9:0] row address setup to RAS# asserted
MA[9:0] row address hold from RAS# asserted
RAS# precharge
RAS# pulse width
RAS# asserted to LCAS#, UCAS# asserted
MA[9:0] column address setup to LCAS#, UCAS# asserted
MA[9:0] column address hold from LCAS#, UCAS#
asserted
LCAS#, UCAS# asserted to RAS# negated
LCAS#, UCAS# pulse width
MD[15:0] read data setup to LCAS#, UCAS# negated
MD[15:0] read data hold from LCAS#, UCAS# negated
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
MD[15:0]
MA[9:0]
RAS#
LCAS#
UCAS#
Table 0-25 DRAM Read Cycle Timing - Non-Page Mode
Parameter
t3
t1
row
X12-SP-001-07
t2
t5
t6
Modesource: 8106_dram_read_npm_01.can
t4
column
t8
2.5Ts+1
t9
1.5Ts-5
2Ts-10
Ts-12
0.5Ts
Ts-15
Ts+1
Ts+2
t7
Ts-3
Min
12
0
t10
valid
t11
Typ
2.5Ts+10
Max
411-1.0
Units
SPC8106
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns