SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 158

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

The sprite and hardware cursor functions share common logic and cannot be displayed simulta-
neously. The following table defines the usage of the bits in off-screen memory representing the
sprite or hardware cursor image:
The pixel bits are packed in memory in the following configuration:
where:
LCD Gray Scale/Color Lookup Table Registers
The LCD Gray Scale/Color Lookup Table (LUT) Registers are provided for mapping pixels to gray
scale values on a monochrome LCD display, and to color values on a color LCD display. For CRT
modes, an external RAMDAC interface is provided. The LUT Registers share the same I/O
address space as the external VGA RAMDAC, namely I/O addresses 3C6h, 3C8h, and 3C9h.
Reads from these addresses will result in accesses to either the internal LUT or the external
RAMDAC depending on the setting of the External DAC Read Select bit in AUX[0B] bit 2. If this bit
is set to 0, then reads will access the internal LUT registers. If this bit is 1, then reads will access
the external RAMDAC registers. For CRT modes, this bit should be set to 1. Note however that
the External DAC RS2 Bit (AUX[0B] bit 3) must be set to 0 in order to allow accesses to the inter-
nal 256 VGA palette locations in the LUT registers. If AUX[0B] bit 3 is set to 1, then these 256
VGA palette locations in the internal LUT cannot be read or written.
I/O writes to the external RAMDAC registers and the internal LUT registers can be disabled by
setting bits 7 and 6 of AUX[0B].
Hardware Functional Specification
Plane/
Cursor
Bit
0/(Bit 0)
1/(Bit 1)
2/(Bit 0)
3/(Bit 1)
SP1-116
Sprite/HW Cursor Bit Definitions
Pixel bit 1 Pixel bit 0 Sprite Pixel Displayed
a. When CRT is enabled, the RAMDAC Index is inverted. The color is not inverted.
0
0
1
1
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
B7
X
X
0
0
8
8
= Displayed Pixel X
B6
1
1
9
9
0
1
0
1
B5
10
10
2
2
CRTC[38] bits 1,0 = 00
Sprite Palette Entry 0
Sprite Palette Entry 1
Sprite Palette Entry 2
Sprite Palette Entry 3
Table 0-59 Pixel Bit Memory Packing Configuration
Address X
B4
11
11
Table 0-58 Sprite/HW Cursor Bit Definitions
3
3
B3
12
12
4
4
B2
13
13
5
5
B1
14
14
6
6
X12-SP-001-07
CRTC[38] bits 1,0 = 01
Sprite Pixel Displayed
Screen
Sprite Palette Entry 1
Sprite Palette Entry 2
Sprite Palette Entry 3
B0
15
15
7
7
B7
16
16
24
24
B6
17
17
25
25
B5
18
18
26
26
Address X+1
CRTC[38] bits 1 = 1
Cursor Pixel Displayed
Cursor Background
Cursor Foreground
Screen
NOT Screen
B4
19
19
27
27
B3
20
20
28
28
a
B2
21
21
29
29
B1
22
22
30
30
411-1.0
SPC8106
B0
23
23
31
31