adc1112d125 NXP Semiconductors, adc1112d125 Datasheet - Page 11

• Manufacturer Part Number: adc1112d125
• Description: Adc1112d125 Dual 11-bit Adc; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 8.
[1]
[2]
[3]
ADC1112D125
Product data sheet
Symbol
Clock timing input: pins CLKP and CLKM
f
t
δ
t
t
CMOS mode timing: pins DA10 to DA0, DB10 to DB0 and DAV
t
t
t
t
t
LVDS DDR mode timing: pins DA9_DA10_P to LOW_DA0_P, DA9_DA10 M to LOW_DA0_M,
DB9_DB10_P to LOW_DB0_P, DB9_DB10_M to LOW_DB0_M, DAVP and DAVM
t
t
t
t
t
clk
lat(data)
d(s)
wake
PD
su
h
r
f
PD
su
h
r
f
clk
Typical values measured at V
range T
specified.
Measured between 20 % to 80 % of V
Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV.
amb
Clock and digital output timing characteristics
= −40 °C to +85 °C at V
Parameter
clock frequency
data latency time
clock duty cycle
sampling delay time
wake-up time
propagation delay
set-up time
hold time
rise time
fall time
propagation delay
set-up time
hold time
rise time
fall time
10.2 Clock and digital output timing
DDA
= 3 V, V
DDA
DDO
= 3 V, V
DDO
.
All information provided in this document is subject to legal disclaimers.
= 1.8 V, T
DDO
= 1.8 V; V
Conditions
DCS_EN = 1
DCS_EN = 0
DATA
DAV
DAV
DATA
DATA
DAV
DAV
DATA
DAV
DATA
DATA
Rev. 2 — 3 March 2011
amb
= 25 °C; minimum and maximum values are across the full temperature
INAP
[1]
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
− V
INAM
= −1 dBFS; V
[2]
[2]
[3]
[3]
Min
100
-
30
45
-
-
-
-
-
-
0.5
0.5
0.5
-
-
-
-
50
50
50
50
INBP
− V
INBM
ADC1112D125
Typ
-
14
50
50
0.8
76
3.9
4.2
5.7
1.4
-
-
-
3.9
4.2
1.4
2.0
100
100
100
100
= −1 dBFS; unless otherwise
Max
125
-
70
55
-
-
-
-
-
-
2.4
2.4
2.4
-
-
-
-
200
200
200
200
© NXP B.V. 2011. All rights reserved.
Unit
MHz
clock
cycles
%
%
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
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