adc1112d125 NXP Semiconductors, adc1112d125 Datasheet - Page 41
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adc1112d125
Manufacturer Part Number
adc1112d125
Description
Adc1112d125 Dual 11-bit Adc; Cmos Or Lvds Ddr Digital Outputs
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1112D125.pdf
(41 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
adc1112d125HN
Manufacturer:
ADI
Quantity:
170
NXP Semiconductors
17. Contents
1
2
3
4
5
6
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
7
8
9
10
10.1
10.2
10.3
10.4
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal characteristics . . . . . . . . . . . . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Application information. . . . . . . . . . . . . . . . . . 16
LVDS DDR outputs selected. . . . . . . . . . . . . . . 5
Clock and digital output timing . . . . . . . . . . . . 11
Device control . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating mode selection. . . . . . . . . . . . . . . . 16
Selecting the output data format. . . . . . . . . . . 17
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Programmable full-scale . . . . . . . . . . . . . . . . . 21
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 22
Equivalent input circuit . . . . . . . . . . . . . . . . . . 23
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 24
Digital output buffers: CMOS mode . . . . . . . . 24
Digital output buffers: LVDS DDR mode . . . . . 25
DAta Valid (DAV) output clock . . . . . . . . . . . . 26
OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 26
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CMOS outputs selected . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical characteristics . . . . . . . . . . . . . . . . . . 14
SPI and Pin control modes . . . . . . . . . . . . . . . 16
Selecting the output data standard . . . . . . . . . 16
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 17
System reference and power management . . 19
Internal/external references . . . . . . . . . . . . . . 19
Common-mode output voltage (V
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 24
Clock input divider . . . . . . . . . . . . . . . . . . . . . 24
O(cm)
) . . . . . 21
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
11.5.6
11.5.7
11.6
11.6.1
11.6.2
11.6.3
12
13
14
15
15.1
15.2
15.3
15.4
16
17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 36
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history . . . . . . . . . . . . . . . . . . . . . . . 38
Legal information . . . . . . . . . . . . . . . . . . . . . . 39
Contact information . . . . . . . . . . . . . . . . . . . . 40
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . 27
Output codes versus input voltage. . . . . . . . . 27
Serial Peripheral Interface (SPI) . . . . . . . . . . 27
Register description . . . . . . . . . . . . . . . . . . . . 27
Default modes at start-up. . . . . . . . . . . . . . . . 28
Register allocation map . . . . . . . . . . . . . . . . . 30
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADC1112D125
Document identifier: ADC1112D125
Date of release: 3 March 2011
All rights reserved.