adc1112d125 NXP Semiconductors, adc1112d125 Datasheet - Page 28

• Manufacturer Part Number: adc1112d125
• Description: Adc1112d125 Dual 11-bit Adc; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1112D125
Product data sheet
Fig 32. SPI mode timing
SCLK
SDIO
CS
R/W W1
11.6.2 Default modes at start-up
W0
A12 A11 A10
Table 17.
[1]
[2]
Table 18.
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on pin CS triggers a transition to SPI control mode. When the
ADC1112D125 enters SPI control mode, the output data standard (CMOS/LVDS DDR) is
determined by the level on pin SDIO (see
output data standard can be changed via bit LVDS_CMOS
Bit
Description
W1
0
0
1
1
1. A falling edge on pin CS in combination with a rising edge on pin SCLK determine the
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
4. A rising edge on pin CS indicates the end of data transmission.
Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
Bits W1 and W0 indicate the number of bytes to be transferred (see
start of communications.
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
A9
Instruction bytes
A8
Instruction bytes for the SPI
Number of data bytes to be transferred after the instruction bytes
W0
0
1
0
1
A7
A6
All information provided in this document is subject to legal disclaimers.
A5
MSB
7
A7
R/W
1 byte
2 bytes
3 bytes
4 bytes or more
Number of bytes transferred
A4
[1]
Rev. 2 — 3 March 2011
A3
A2
6
W1
A6
A1
[2]
A0
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
D7
5
W0
A5
D6
[2]
D5
Figure
Register N (data)
4
A12
A4
D4
D3
33). Once in SPI control mode, the
D2
3
A11
A3
D1
D0
Table
(see
ADC1112D125
D7
2
A10
A2
D6
18).
Table 24
D5
Register N + 1 (data)
D4
© NXP B.V. 2011. All rights reserved.
D3
1
A9
A1
).
D2
D1
005aaa086
D0
LSB
0
A8
A0
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