adc1112d125 NXP Semiconductors, adc1112d125 Datasheet - Page 26

• Manufacturer Part Number: adc1112d125
• Description: Adc1112d125 Dual 11-bit Adc; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1112D125
Product data sheet
11.5.3 DAta Valid (DAV) output clock
11.5.4 OuT-of-Range (OTR)
11.5.5 Digital offset
Table 14.
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1112D125. Detailed timing diagrams for CMOS and LVDS DDR
modes are provided in
recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100;
see
An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for
ADC channel B. The latency of OTRA/OTRB is fourteen clock cycles. The OTR response
can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see
mode, the latency of OTRA/OTRB is reduced to only four clock cycles (per ADC channel).
The Fast OTR detection threshold (below full-scale) can be programmed via bits
FASTOTR_DET[2:0].
Table 15.
By default, the ADC1112D125 delivers output code that corresponds to the analog input.
However, it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see
LVDS_INT_TER[2:0]
000
001
010
011
100
101
110
111
FASTOTR_DET[2:0]
000
001
010
011
100
101
110
111
Table
25).
LVDS DDR output register 2
Fast OTR register
All information provided in this document is subject to legal disclaimers.
Figure 4
Rev. 2 — 3 March 2011
Table
26).
and
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Figure 5
respectively. In LVDS DDR mode, it is highly
Resistor value (Ω)
no internal termination
300
180
110
150
100
81
60
Detection level (dB)
−20.56
−16.12
−11.02
−7.82
−5.49
−3.66
−2.14
−0.86
ADC1112D125
© NXP B.V. 2011. All rights reserved.
Table
30). In this
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