adc1112d125 NXP Semiconductors, adc1112d125 Datasheet - Page 29

• Manufacturer Part Number: adc1112d125
• Description: Adc1112d125 Dual 11-bit Adc; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1112D125
Product data sheet
When the ADC1112D125 enters SPI control mode, the output data format (two’s
complement or offset binary) is determined by the level on pin SCLK (gray code can only
be selected via the SPI). Once in SPI control mode, the output data format can be
changed via bit DATA_FORMAT[1:0] (see
Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
(CMOS LVDS DDR)
(CMOS LVDS DDR)
All information provided in this document is subject to legal disclaimers.
SDIO
SDIO
CS
CS
Rev. 2 — 3 March 2011
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Table
Offset binary, LVDS DDR
default mode at start-up
two's complement, CMOS
default mode at start-up
24).
ADC1112D125
© NXP B.V. 2011. All rights reserved.
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