adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet - Page 11

• Manufacturer Part Number: adsp-21msp58
• Description: Dsp Microcomputers
• Manufacturer: Analog Devices, Inc.

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Autobuffering
In some applications, it is advantageous to perform block data
transfers between the analog converters and processor memory.
Analog interface autobuffering enables the automatic transfer of
data blocks directly from the ADC to on-chip processor data
memory or from on-chip processor data memory directly to the
DAC.
ADC and DAC Interrupts
The analog interface generates two interrupts that signal either:
(1) a 16-bit, 8 kHz analog-to-digital or digital-to-analog conver-
sion has been completed, or (2) an autobuffer block transfer
has been completed (i.e., the data buffer contents have been
received or transferred).
When an analog interrupt occurs, the processor vectors to the
addresses listed in Table II, Interrupt Priority & Interrupt Vector
Addresses.
The ADC receive and DAC transmit interrupts occur at an
8 kHz rate, indicating when the data registers should be ac-
cessed. On the receive side, the ADC interrupt is generated each
time an A/D conversion cycle is completed and the 16-bit data
word is available in the ADC receive register. On the transmit
side, the DAC interrupt is generated each time an D/A conver-
sion cycle is completed and the DAC transmit register is ready
for the next 16-bit data word.
Both interrupts are generated simultaneously at an 8 kHz rate,
occurring every 3250 instruction cycles with a 13 MHz internal
processor clock. The interrupts are generated continuously,
starting when the analog interface is powered up by setting the
AX0 AX1 AY0 AY1
I0
I1
I2
I3
AR
DAG 1
ALU
M0
M1
M2
M3
AF
L0
L1
L2
L3
I4
I5
I6
I7
DAG 2
M4
M5
M6
M7
MX0 MX1 MY0 MY1
MR0 MR1 MR2 MF
L4
L5
L6
L7
MAC
OWRCNTR
SSTAT
COUNT
STACK
CNTR
4 x 14
PROGRAM SEQUENCER
S I
STATUS
STACK
SR0
MSTAT
12 x 25
ICNTL
IMASK
ASTAT
SHIFTER
IFC
SE
SR1
SB
Figure 9. ADSP-21msp58/59 Registers
STACK
STACK
16 x 14
LOOP
4 x 18
14
14
24
16
PC
CONTROL REGISTERS
ANALOG INTERFACE
0x3FEC
PMA BUS
DMA BUS
PMD BUS
DMD BUS
0x3FEE-0x3FEF
DAC
0x3FFF
0x3FFE
0x3FED
ADC
SYSTEM CONTROL
DM WAIT CONTROL
–11–
CONTROL REGISTERS
0x3FFA-0x3FF3
APWD bits (Bits 5 and 6) to one in the analog control register.
Because both interrupts occur simultaneously, only one should
be enabled (in IMASK) to vector to a single service routine that
handles transmit and receive data. However, when using
autobuffer transfers, both interrupts should be enabled.
ADSP-21msp58/59 REGISTERS
Figure 9 summarizes the ADSP-21msp58/59 registers. Some
registers store values. For example, AX0 stores an ALU oper-
and; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the number of wait states for different zones of data
memory.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The bit and field definitions for control and status registers are
given in the rest of this section, except IMASK, ICNTL, and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory locations; that is, you access these
registers by reading and writing data memory locations rather
than register names. The particular data memory address is
shown with each memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeter-
minate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
SPORT 0
RX0
TX0
PROGRAM
2K x 24
SRAM
PX
CONTROL REGISTERS
0x3FF2-0x3FEF
SPORT 1
RX1
ADSP-21msp59
PROGRAM
4K x 24
TX1
ONLY
ROM
ADSP-21msp58/59
2K x 16
SRAM
DATA
0x3FFD
0x3FFC
0x3FFB
TIMER
TPERIOD
TCOUNT
TSCALE
0x3FE0-0x3FE5
0x3FE6-0x3FE7
0x3FE8
INTERFACE
HOST
PORT
POWERDOWN
CONTROL
LOGIC
FLAG
DATA
STATUS
HMASK