adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet - Page 4

• Manufacturer Part Number: adsp-21msp58
• Description: Dsp Microcomputers
• Manufacturer: Analog Devices, Inc.

FO (DT1)
FL0
V
ADSP-21msp58/59
Pin
Group
Name
IRQ0 (RFS1) 1
IRQ1 (TFS1) 1
SCLK1
FI (DR1)
GND
PWD
Analog Pins
VIN
VIN
Decouple
VOUT
VOUT
V
REF_
FILTER
V
GND
Host Interface Port
The ADSP-21msp58/59 host interface port (HIP) is a parallel
I/O port that allows for an easy connection to a host processor.
Through the HIP, the ADSP-21msp58/59 can be used as a
memory-mapped peripheral to a host computer. The HIP can
be thought of as an area of dual-ported memory, or mailbox reg-
isters, that allows communication between the computational
core of the ADSP-21msp58/59 and the host computer.
The host interface port is completely asynchronous. The host
processor can write data into the HIP while the ADSP-
21msp58/59 is operating at full speed.
The HIP can be configured with the following pins:
• BMODE (when MMAP = 0) determines whether the ADSP-
• HMD0 configures the bus strobes as separate read and write
• HMD1 selects separate address (3-bit) and data (8-bit) buses,
21msp58/59 boots from the host processor (through the HIP)
or external EPROM (through the data bus).
strobes, or a single read/write select and a host data strobe.
or a multiplexed 8-bit address/data bus with address latch
enable.
DD
REF
CC
NORM
AUX
A
P
N
1
1
1
1
#
of
Pins Output Function
1
1
4
5
1
1
1
1
1
1
1
2
Input/
I
I
O
I
O
O
I
I
I
I
O
O
O
O
External interrupt request #0
External interrupt request #1
Programmable clock output
Flag input pin
Flag output pin
General purpose flag output pin
Digital power supply pins
Ground pins
Powerdown pin
Input terminal of the NORM
amplifier for the encoder section
(ADC)
Input terminal of the AUX
amplifier for the encoder section
(ADC)
Ground reference of the NORM
and AUX amplifiers for the
encoder section (ADC)
Noninverting output terminal of
the differential amplifier from
the decoder section (DAC)
Inverting output terminal of the
differential amplifier from the
decoder section (DAC)
Output voltage reference
Voltage reference external by-
pass filter node
Analog power supply
Analog ground
–4–
Tying these pins to appropriate values configures the ADSP-
21msp58/59 for straight-wire interface to a variety of industry-
standard microprocessors and microcomputers.
When the host processor writes an 8-bit value to the HIP, the
upper eight bits of the HIP registers are all zeros. For additional
information, refer to the ADSP-2100 Family User’s Manual,
Chapter 7, for information about 8-bit configuration.
HIP Operation
The HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. The HIP
data registers are memory-mapped in the internal data memory
of the ADSP-21msp58/59. HIP transfers can be managed using
either interrupts or polling. These registers are shown in the sec-
tion “ADSP-21msp58/59 Registers.” The two status registers
provide status information to both the ADSP-21msp58/59 and
the host processor. HSR7 contains a software reset bit that can
be set by the ADSP-21msp58/59 and the host.
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-21msp58/59 cycles.
The HIP generates an interrupt whenever an HDR register re-
ceives data from a host processor write. It also generates an in-
terrupt when the host processor has performed a successful read
of any HDR. The read/write status of the HDRs is also stored in
the HSR registers.
The HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the HDR4 Write bit in
HMASK and the HIP Write interrupt enable bit in IMASK are
set.
The HIP provides a second method of booting the ADSP-
21msp58/59 in which the host processor loads instructions into
the HIP. The ADSP-21msp58/59 automatically transfers the
data, in this case opcodes, to internal program memory. The
BMODE pin determines whether the ADSP-21msp58/59 boots
from the host processor through the HIP or from external
EPROM over the data bus.
Interrupts
The interrupt controller lets the processor respond to interrupts
and reset with a minimum of overhead. The ADSP-21msp58/59
provides up to three external interrupt input pins, IRQ0, IRQ1,
and IRQ2. IRQ2 is always available as a dedicated pin;
SPORT1 may be reconfigured for IRQ1 and IRQ0 and the flag.
The ADSP-21msp58/59 also supports internal interrupts from
the timer, the host interface port, the serial ports, the analog in-
terface, and the powerdown control circuit. The interrupts are
internally prioritized and individually maskable (except for
powerdown and RESET). The input pins can be programmed
for either level- or edge-sensitivity. The priorities and vector ad-
dresses for the interrupts are shown in Table II; the interrupt
registers are shown in Figure 2.
REV. 0