adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet - Page 9

• Manufacturer Part Number: adsp-21msp58
• Description: Dsp Microcomputers
• Manufacturer: Analog Devices, Inc.

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“System Interface” for detailed information about the power-
down feature.
• Powerdown mode holds the processor in CMOS standby with
• Quick recovery from powerdown. In some modes, the proces-
• Support for an externally generated TTL or CMOS processor
• Support for crystal operation includes disabling the oscillator
• Powerdown is initiated by either the powerdown pin (PWD)
• Interrupt support allows an unlimited number of instructions
• Context clear/save control lets the processor continue where it
• The RESET pin also can be used to terminate powerdown,
• Setting the CLKODIS bit (Bit 14 of the SPORT0 Autobuffer
Idle
When the ADSP-21msp58/59 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruction.
Slow Idle
The IDLE instruction is enhanced on the ADSP-21msp58/59 to
let the processor’s internal clock signal be slowed, further reduc-
ing power consumption. The reduced clock frequency, a pro-
grammable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, and timer clock, are reduced by the same ratio.
CLKOUT remains at the normal rate; it is not reduced. The de-
fault form of the instruction, when no clock divisor is given, is
the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts––the 1-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-21msp58/59 remains in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
a maximum current of less than 100 A in some modes.
sor can begin executing instructions in less than 100 CLKIN
cycles.
clock. The external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLKIN cycle recovery.
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and
letting the oscillator run to allow 100 CLKIN cycle start-up.
or the software powerdown force bit.
to be executed before optionally powering down. The power-
down interrupt also can be used as a non-maskable, edge-
sensitive interrupt.
left off or start with a clean context when leaving the power-
down state.
and the host software reset feature can be used to terminate
powerdown under certain conditions.
Control Register [0x3FF3]) disables the CLKOUT pin during
powerdown.
–9–
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
Standalone ROM Execution (ADSP-21msp59 Only)
When the MMAP and BMODE pins both are set to 1, the
ROM is automatically enabled and execution commences from
program memory location 0x0800 at the start of ROM. This
feature lets an embedded design operate without external
memory components. To operate in this mode, the ROM coded
program must copy an interrupt vector table to the appropriate
locations in program memory RAM. In this mode, the ROM
enable bit defaults to 1 during reset.
MMAP = 0
MMAP = 1
Ordering Procedure For ADSP-21msp59 ROM Processors
To place an order for a custom ROM-coded ADSP-21msp59
processor, you must:
1. Complete the following forms contained in the ADSP ROM
2. Return the forms to Analog Devices along with two copies of
3. Place a purchase order with Analog Devices for nonrecurring
After this information is received, it is entered into Analog
Devices’ ROM Manager System that assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
Ordering Package, available from your Analog Devices sales
representative:
ADSP-21msp59 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Preproduction ROM Products
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).
engineering changes (NRE) associated with ROM product
development.
BMODE = 0
Boot from EPROM,
then execution starts
at internal RAM
location 0x0000
No booting, execution
starts at external memory execution starts at
location 0x0000
Table III. Boot Summary Table
ADSP-21msp58/59
BMODE = 1
Boot from HIP, then
execution starts at
internal RAM location
0x0000
Stand Alone Mode,
internal ROM location
0x0800