adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet - Page 18

• Manufacturer Part Number: adsp-21msp58
• Description: Dsp Microcomputers
• Manufacturer: Analog Devices, Inc.

Permissible yops (base instruction set)
AY0, AY1, AF
Permissible yops and constants (extended instruction set)
AY0, AY1, AF, 0, 1, 2, 3, 4, 5, 7, 8, 9, 15, 16, 17, 31, 32, 33,
63, 64, 65, 127, 128, 129, 255, 256, 257, 511, 512, 513, 1023,
ADSP-21msp58/59
Syntax:
Description: Executing the ENA INTS instruction allows all
The interrupt disable instruction source code is specified as
follows:
Syntax:
Description: Reset enables interrupt servicing. Executing the
Extended ALU and Multiplier Operations
The following extended computation operations are available
only on the ADSP-21msp58/59 processor. The term “base in-
struction set” refers to the computations and instructions avail-
able on all ADSP-21xx processors.
Additional Constants for ALU Operations
A new set of numerical constants may be used in all nonmulti-
function ALU operations (except DIVS and DIVQ) using both
X and Y operands. The instruction source code is specified as
follows:
Syntax: [IF condition]
Permissible xops
AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1
Permissible functions
ADD/ADD with CARRY, SUBTRACT X–Y/SUBTRACT X–
Y with BORROW, SUBTRACT Y–X/SUBTRACT Y–X with
BORROW, AND, OR, XOR
Permissible yops (base instruction set)
AY0, AY1, AF
Permissible yops and constants (extended instruction set)
AY0, AY1, AF, 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024,
2048, 4096, 8192, 16384, 32767, –2, –3, –5, –9, –17, –33, –65,
–129, –257, –513, –1025, –2049, –4097, –8193, –16385, –32768
Examples:
Description: Test the optional condition and, if true, perform
Additional Constants for ALU PASS Operation
A new set of numerical constants may be used in the PASS in-
struction. The instruction source code is specified as follows:
Syntax: [IF condition]
ENA INTS;
DIS INTS;
unmasked interrupts to be serviced again.
DIS INTS instruction causes all interrupts to be
masked without changing the contents of the
IMASK register. Disabling interrupts does not
affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
AR = AR+1;
AR = MR1 - 33;
IF GT AF = AX1 OR 16;
the specified function. If false then perform a no-
operation. Omitting the condition performs the
function unconditionally. The operands are con-
tained in the data registers specified in the in-
struction or optionally a constant may be used.
AR
AF
AR
AF
= xop function
= pass
yop
constant
yop
constant
–18–
1024, 1025, 2047, 2048, 2049, 4095, 4096, 4097, 8191, 8192,
8193, 16383, 16384, 16385, 32766, 32767, –1, –2, –3, –4, –5,
–6, –8, –9, –10, –16, –17, –18, –32, –33, –34, –64, –65, –66, –128,
–129, –130, –256, –257, –258, –512, –513, –514, –1024, –1025,
–1026, –2048, –2049, –2050, –4096, –4097, –4098, –8192, –8193,
–8194, –16384, –16385, –16386, –32767, –32768
Examples:
Description: Test the optional condition and, if true, pass the
Note:
ALU Bit Operations
The additional constants for ALU operations allow you to code
bit test, set, clear, and toggle operations through careful choice
of the constant and ALU function. For streamlined programming,
the source code for these operations can also be specified as:
Syntax: [IF condition]
Permissible xops
AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1
Permissible n Values (0 = LSB)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
Examples:
Definitions of Operations
TSTBIT is an AND operation with a 1 in the selected bit
SETBIT is an OR operation with a 1 in the selected bit
CLBIT is an AND operation with a 0 in the selected bit
TGBIT is an XOR operation with a 1 in the selected bit
Result-Free ALU Operations
The result-free ALU operations allow the generation of condi-
tion flags based on an ALU operation but discard the result.
The source code for the instruction is specified as follows:
Syntax:
where <ALU> is any unconditional ALU operation of the 21xx
base instruction set (except DIVS or DIVQ). (Note that the addi-
tional constant ALU operations of the ADSP-2171/2181 ex-
tended instruction set are not allowed.)
NONE = <ALU>;
IF GE AR = PASS AY0;
IF EQ AF = PASS –1025;
source operand unmodified through the ALU
block and store in the destination location. If the
condition is not true, perform a no-operation.
Omitting the condition performs the pass uncon-
ditionally. The source operand is contained in
the data registers specified in the instruction or
optional constant.
The PASS instruction performs the transfer to the
AR register and affect the status flag; this instruc-
tion is different from a register move operation
which does not affect any status flags. PASS 0 is
one method of clearing AR. PASS 0 can also be
combined in a multifunction instruction in con-
junction with memory reads and writes to clear AR.
The ALU status flags (in the ASTAT register)
are not defined for the execution of this instruc-
tion when using the constant values other than 0,
1, and –1.
AF=TSTBIT 5 of AR;
IF NE JUMP SET;
/* JUMP TO SET IF BIT IS SET */
AR
AF
=
TSTBIT n of xop;
SETBIT n of xop;
CLBIT n of xop;
TGBIT n of xop;
REV. 0