adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet - Page 19

• Manufacturer Part Number: adsp-21msp58
• Description: Dsp Microcomputers
• Manufacturer: Analog Devices, Inc.

REV. 0
Examples:
Description: Perform the designated ALU operation, set the
MAC Operations
A modified MAC operation allows additional type 9 instruc-
tions. The conditional ALU/MAC instruction has been modi-
fied to allow the X operand to be used as the Y operand as well.
This allows a single cycle X
The new MAC instructions allow the use of any xop as both the
X and Y operands. The instructions source code is specified as
follows:
Syntax: [IF condition]
Permissible xops
AR, MR0, MR1, MR2, MX0, MX1, SR0, SR1
Example:
Note:
Biased Rounding
A new mode has been added to allow biased rounding in addi-
tion to the normal unbiased rounding. When the BIASRND bit
is set to 0 the normal unbiased rounding operations occur.
When the BIASRND bit is set to 1, biased rounding occurs in-
stead of the normal unbiased rounding. When operating in bi-
ased rounding mode all rounding operations with MR0 set to
0x8000 will round up, rather than only rounding odd MR1
values up. For example:
MR value before RND
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000, all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit speci-
fied algorithms which specify biased rounding such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note:
Interrupt Enable
The ADSP-21msp58/59 supports an interrupt enable instruc-
tion. Interrupts are enabled by default at reset. The instruction
source code is specified as follows:
Syntax:
Description:
Interrupt Disable
The ADSP-21msp58/59 supports an interrupt disable instruc-
tion. The instruction source code is specified as follows:
Syntax:
Description:
BIASRND bit is bit twelve of the SPORT0
Autobuffer Control register.
NONE = AX0 – AY0;
NONE = PASS SR0;
condition flags, then discard the result value.
This allows the testing of register values without
disturbing the AR or AF register values.
IF LT MR=MR+ SR0 * SR0 (SS);
Both X operators must be the same register.
Reset enables interrupt servicing. Executing the
DIS INTS instruction causes all interrupts to
Executing the ENA INTS instruction allows
all unmasked interrupts to be serviced again.
ENA INTS;
DIS INTS;
biased RND result
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
MR
MF
2
, and also X
=
[MR +]
[MR –]
2
operations.
unbiased RND result
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
xop * yop (UU);
xop (SS) ;
(RND);
–19–
CIRCUIT DESIGN CONSIDERATIONS
The following sections discuss interfacing analog signals to the
ADSP-21msp58/59.
Analog Signal Input
Figure 10 shows the recommended input circuit for the analog in-
put pin (either VIN
implements a first-order low-pass filter (R1C1) with a 3 dB point
less than 40 kHz. This is the only filter required external to the
processor to prevent aliasing of the sampled signal. Since the
ADSP-21msp58/59’s sigma-delta ADC uses a highly oversampled
approach that transfers the bulk of the anti-aliasing filtering into the
digital domain, the off-chip anti-aliasing need only be of low order.
The on-chip ADC PGA can be used when there is not enough
gain in the input circuit. The PGA gain is set by bits 9 and 0
(IG1, IG0) of the processor’s analog control register. The gain
must be chosen to ensure that a full-scale input signal (at R1 in
Figure 10) produces a signal level at the input to the sigma-delta
modulator of the ADC that does not exceed VIN
the “Analog Interface Electrical Characteristics” specifications).
VIN
age (nominal of 2.5 V) of the ADSP-21msp58/59, which lets the
analog section of the processor operate from a single supply.
The input signal should be ac-coupled with an external capaci-
tor (C2). The value of C2 is determined by the input resistance
of the analog input (VIN
sired cutoff frequency. The cutoff frequency should be 30 Hz.
The following equation should be used to determine the values
of R1, C1, and C2; R1 should be 2.2 k . C2 should be 0.027
R
f
For optimum ADC performance, C1 should be an NPO type
capacitor.
*If minimum (<0.1 dB) rolloff at 4 kHz is desired, f
1
F; C3 should be equal to C2.
IN
= cutoff frequency <30 Hz
SOURCE
= ADSP-21msp58/59 input resistance (200 k )
INPUT
NORM
Figure 10. Recommend Analog Input Circuit
and VIN
GROUND
STAR
R1
be masked without changing the contents of the
IMASK register. Disabling interrupts does not af-
fect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
NORM
AUX
f
2
C1
> 20 kHz < 40 kHz*
are biased at the Internal Reference Volt-
or VIN
C2
NORM
R1
C1
R1
C3
C2
ADSP-21msp58/59
, VIN
2
2 f
2 f
AUX
2.2 k
f
1
1
1
VIN
1
). The circuit of Figure 10
VIN
DECOUPLE
2
2
AUX
R
C1
R1
NORM
AUX
IN
ADSP-21msp58/59
) (200 k ) and the de-
2
should be set to 40 kHz.
MUX
MAX
PGA
(refer to