adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet - Page 6

• Manufacturer Part Number: adsp-21msp58
• Description: Dsp Microcomputers
• Manufacturer: Analog Devices, Inc.

CLKOUT signal is enabled and disabled by the CLKODIS bit
in the SPORT0 Autobuffer Control Register, DM[0x3FF3].
Because the ADSP-21msp58/59 includes an on-chip oscillator
circuit, an external crystal may also be used. The crystal should
be connected across the CLKIN and XTAL pins, with two ca-
pacitors connected as shown in Figure 4. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
Reset
The RESET signal initiates a master reset of the ADSP-
21msp58/59. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET dur-
ing initial power-up must be held long enough to allow the
processor’s internal clock to stabilize. If RESET is asserted at
any time after power-up, the clock continues to run and does
not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
plied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
ADSP-21msp58/59
Figure 4. External Crystal Connections
CLKIN
ADSP-21msp58/59
A
PROGRAM
CLKOUT
(OPTIONAL)
CLKIN XTAL V
RESET
IRQ2
BR
BG
MMAP
FL0
MEMORY
CLOCK OR
CRYSTAL
NOTE: The two MSBs of the Boot EPROM Address are also the two MSBs of the Data Bus.
This is only for the 27C256 and 27C512.
D
XTAL
24
PMS
CS
Figure 3. ADSP-21msp58/59 Basic System Configuration
WE
OE
CC
1
CLKOUT
GND
ADSP-21msp58/59
ANALOG
2
RD
INPUT
A
3
WR
ANALOG
OUTPUT
DD
ADDRESS
OE
WE
4
is ap-
PERIPHERALS
A
V
14
MEMORY &
DD
(OPTIONAL)
4
DATA
GND HOST
DATA DMS
D
2 3 - 8
5
D
–6–
24
16
MODE
CS
3
2000 CLKIN cycles will ensure that the PLL has locked (this
does not, however, include the crystal oscillator start-up time).
During this power-up sequence, the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, t
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an ex-
ternal Schmidt trigger is recommended.
The master RESET sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus re-
quest and the chip is configured for booting (MMAP = 0), the
boot loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000 and ex-
ecution begins.
Program Memory Interface
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single exter-
nal data bus and a single external address bus. The data and
address busses are three-stated when the DSP runs from inter-
nal memory. Refer to the ADSP-2100 Family User’s Manual,
Chapter 10, “Memory Interface” for a detailed explanation. The
14-bit address bus directly addresses up to 16K words. See
“Program Memory Maps” for details on program memory
addressing.
The program memory data lines are bidirectional. The program
memory select (PMS) signal indicates access to program
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and is used as a write strobe.
SERIAL
PORT 0
SERIAL
PORT 1
7
HIP
BMS
8
HIP CONTROL
HIP DATA/ADDR
SCLK
RFS OR IRQ0
TFS OR IRQ1
DT OR FO
DR OR FI
DR
SCLK
RFS
TFS
DT
OE
14
A
D
2 3 - 2 2
e.g., EPROM
MEMORY
27C64
27C128
27C256
27C512
2
BOOT
SERIAL DEVICE
SERIAL DEVICE
D
PROCESSOR
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
1 5 - 8
D
8
HOST
CS
RSP
.
REV. 0