adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet - Page 35

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adsp-21msp58

Manufacturer Part Number
adsp-21msp58
Description
Dsp Microcomputers
Manufacturer
Analog Devices, Inc.
Datasheet
REV. 0
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
Package
TQFP
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
P
graph (Figure 25).
(C
Address, DMS
Data Output, WR 9
RD
CLKOUT
Total power dissipation for this example is P
Typical Power Consumption
The typical power consumption can be calculated from the fol-
lowing data, taken at 5.0 V and +25 C. Dynamic V
taken while executing 80% type 1 multifunction instructions, on
random data.
Parameter
I
I
I
I
I
I
Analog Devices recommends that the ADSP-21msp58/59
is used with a 13 MHz input clock. Below this input clock
DD
DD
DD
DD
DD
CC
INT
T
T
PD = Power Dissipation in W
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
The application operates at V
CA
JA
JC
AMB
CASE
V
= internal power dissipation from Power vs. Frequency
Digital Supply Current (Idle, Codec Powered Up)
Digital Supply Current (Idle)
Digital Supply Current (Dynamic, Codec Powered Up) 83 mA
Digital Supply Current (Dynamic)
Digital Supply Current (Powerdown)
Analog Supply Current (Dynamic)
= Thermal Resistance (Junction-to-Ambient)
= Thermal Resistance (Junction-to-Case)
= Thermal Resistance (Case-to-Ambient)
DD
Total Power Dissipation = P
= T
= Case Temperature in C
2
CASE
f ) is calculated for each output:
– (PD
# of
Pins
8
1
1
50 C/W
JA
C
10 pF
10 pF
10 pF
10 pF
C
CA
)
V
DD
DD
V
5
5
5
5
2
2
2
2
2
INT
DD
= 5.0 V and t
V
V
V
V
2 C/W
2
JC
f
+ (C
f
26 MHz
13 MHz
13 MHz
26 MHz
INT
V
DD
CK
+ 92 mW.
2
= 76.92 ns.
DD
=
=
=
=
f )
data was
48 C/W
CA
52 mW
30 mW
92 mW
Typ
19 mA
13 mA
78 mA
10 A
15 mA
4 mW
6 mW
–35–
frequency, the codec performance changes and the performance
specifications cannot be guaranteed. The codec filter character-
istics, however, scale approximately linearly with frequency.
If the codec is disabled, then the processor can be used at any
allowed input frequency. The power consumption of the ADSP-
21msp58/59 at these frequencies is shown in Figure 25.
VALID FOR ALL TEMPERATURE GRADES.
1
2
3
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-21msp58/59 STATE OF OPERATION DURING EXECUTION OF
IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V
POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.
TYPICAL POWER DISSIPATION AT 5.0V V
INSTRUCTION (CLOCK FREQUENCY REDUCTION). POWER REFLECTS DEVICE
OPERATING WITH CLKOUT DISABLED.
Figure 25. Power vs. Internal Processor Frequency
550
500
450
400
350
300
250
200
150
100
110
100
50
70
60
50
40
30
20
10
90
80
70
60
50
40
30
2
2
2
INTERNAL
(80% NOMINAL LOADING)
CODEC INACTIVE
MAX VALUES
191mW
154mW
118mW
IDLE 0
CODEC INACTIVE
MAX VALUES
21mW
20mW
29mW
57mW
49mW
42mW
IDLEs @ 5.0V
CODEC INACTIVE
TYPICAL VALUES
6
6
6
POWER, IDLE n MODES
POWER, INTERNAL
10
10
10
POWER, IDLE
V
V
DD
DD
1/t
1/t
1/t
14
V
14
14
= 5.5V
CK
DD
= 5.5V
CK
CK
ADSP-21msp58/59
V
– MHz
= 4.5V
DD
– MHz
– MHz
DD
18
18
18
= 4.5V
DURING EXECUTION OF IDLE n
2
1
22
22
22
3
100mW
83mW
69mW
391mW
26
26
26
480mW
310mW
65mW
35mW
37mW
30
30
30
550
500
450
400
350
300
250
200
150
100
IDLE (16)
IDLE (32)
IDLE (64)
IDLE (128)
DD
50
OR GND.

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