z86e72 ZiLOG Semiconductor, z86e72 Datasheet - Page 32

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z86e72

Manufacturer Part Number
z86e72
Description
Otp Microcontroller
Manufacturer
ZiLOG Semiconductor
Datasheet

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Z86E72/73
OTP Microcontroller
28
Port 1 (P17–P10)
Port 1 is a multiplexed Address (A7–A0) and Data (D7–D0), CMOS-compatible
®
port. Port 1 is dedicated to the ZiLOG ZBus
-compatible memory interface. The
operations of Port 1 are supported by the Address Strobe (/AS) and Data Strobe
(/DS) lines and by the Read/Write (R//W) and Data Memory (/DM) control lines.
Data memory read/write operations are done through this port. If more than 256
external locations are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along with Port 0, /AS, /DS, and
R//W, allowing the Z86E7X to share common resources in multiprocessor and
DMA applications. Port 1 can also be configured for standard port output mode.
See
Figure
15.
PS008704-0507

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