z86e72 ZiLOG Semiconductor, z86e72 Datasheet - Page 35

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z86e72

Manufacturer Part Number
z86e72
Description
Otp Microcontroller
Manufacturer
ZiLOG Semiconductor
Datasheet

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PS008704-0507
Port 3 (P37–P31)
The CCP wakes up with the 8 bits of Port 2 configured as inputs with open-drain
outputs.
Port 2 also has an 8-bit input OR and an AND gate that can be used to wake up
the part. P20 can be programmed to access the edge-selection circuitry.
Port 3 is a 7-bit, CMOS-compatible port (see
fixed inputs (P33–P31) and four fixed outputs (P37–P34) and can be configured
under software control for Input/Output, Interrupt, Port handshake, Data Memory
functions, and output from the counter/timers. P31, P32, and P33 are standard
CMOS inputs; outputs are push-pull.
Two on-board comparators process analog signals on P31 and P32 with refer-
ence to the voltage on Pref1 and P33. The analog function is enabled by program-
P33 (PREF2)
P32
P31
PREF1
P34 OUT
P37 OUT
+
-
+
PCON
-
COMP2
COMP1
Figure 16. Port 2 Configuration
Figure 17. Port 3 Configuration
D0
P34 OUT
T8
*
0 = P34, P37 Standard Output
1 = P34, P37 Comparator Output
Reset condition.
Counter/Timer
CTR0
Figure
D0
*
17). Port 3 consists of three
0 Normal Control
1 8-bit Timer output active
OTP Microcontroller
P37
P34
PAD
PAD
31

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