z86e72 ZiLOG Semiconductor, z86e72 Datasheet - Page 71

• Manufacturer Part Number: z86e72
• Description: Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

Z86E72/73
OTP Microcontroller
67
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the compar-
ator outputs to P34 and P37, and a 0 releases the port to its standard I/O configu-
ration.
Port 0 Output Mode (D2)
Bit 2 controls the output mode of Port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop-
Mode Recovery
(Figure
40). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level is required
from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3,
and D4 of the SMR register specify the source of the Stop-Mode Recovery signal.
Bit D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located in
Bank F of the Expanded Register Group at address 0BH.
PS008704-0507