z86e72 ZiLOG Semiconductor, z86e72 Datasheet - Page 68

• Manufacturer Part Number: z86e72
• Description: Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

PS008704-0507
Clock
When more than one interrupt is pending, priorities are resolved by a programma-
ble priority encoder controlled by the Interrupt Priority register. An interrupt
machine cycle is activated when an interrupt request is granted. This disables all
subsequent interrupts, saves the Program Counter and Status Flags, and then
branches to the program memory vector location reserved for that interrupt. All
Z86E7X interrupts are vectored through locations in the program memory. This
memory location and the next byte contain the 16-bit address of the interrupt ser-
vice routine for that particular interrupt request. To accommodate polled interrupt
systems, interrupt inputs are masked and the Interrupt Request register is polled
to determine which of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge
triggered and are programmable by the user. The software can poll to identify the
state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register
(R250), bits D7 and D6. The configuration is indicated in
Table 27. IRQ Register
The Z86E7X on-chip oscillator has a high-gain, parallel-resonant amplifier for con-
nection to a crystal, LC, ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz
maximum, with a series resistance (RS) less than or equal to 100 Ohms. The
Z86E7X on-chip oscillator can be driven with a cost-effective RC network or other
suitable external clock source.
Notes:
F = Falling Edge
R = Rising Edge
In analog mode, the Stop-Mode Recovery sources
selected by the SMR register are connected to the IRQ1
input. Any of the Stop-Mode Recovery sources for SMR
(except P31, P32, and P33) can be used to generate
IRQ1 (falling edge triggered).
D7
0
0
1
1
IRQ
D6
0
1
0
1
IRQ2 (P31)
R/F
F
F
F
Interrupt Edge
IRQ0 (P32)
R/F
R
F
F
Table
OTP Microcontroller
27.
64