z86e72 ZiLOG Semiconductor, z86e72 Datasheet - Page 70

• Manufacturer Part Number: z86e72
• Description: Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

PS008704-0507
HALT
STOP
Port Configuration Register (PCON)
HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/
timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit HALT Mode. After the
interrupt service routine, the program continues from the instruction after the
HALT.
This instruction turns off the internal clock and external crystal oscillation and
reduces the standby current to 10 μA (typical) or less. STOP Mode is terminated
only by a reset, such as WDT time-out, POR, SMR, or external reset. This causes
the processor to restart the application program at address 000CH. To enter
STOP (or HALT) mode, you need to first flush the instruction pipeline to avoid sus-
pending execution in mid-instruction. To do this, you must execute a NOP (op
code = FFH) immediately before the appropriate sleep instruction. For example:
or
The PCON register
located in the expanded register file at Bank F, location 00.
*Default setting after reset
Figure 39. Port Configuration Register (PCON)—Write Only
PCON (0F) 0H
D7 D6 D5 D4 D3 D2 D1 D0
FF
6F
FF
7F
NOP
STOP
NOP
HALT
(Figure
39) configures the comparator output on Port 3. It is
; clear the pipeline
; enter STOP Mode
; clear the pipeline
; enter HALT Mode
Comparator Output Port 3
0 P34, P37, Standard Output*
1 P34, P37, Comparator Output
Reserved (must be 1)
Port 0
0 = Open-drain
1 = Push-pull*
Reserved (must be 1)
OTP Microcontroller
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