mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet

Page 1

... This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. MPC8568EEC Rev. 0, 05/2009 Contents 1. MPC8568E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18 7 ...

Page 2

... Engine 1.1 Key Features Key features of the MPC8568E include: • High-performance Power Architecture™ e500v2 core with 36-bit physical addressing • 512 Kbytes of level-2 cache MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev 512-Kbyte L2 Cache/ SRAM e500 Coherency Core Complex ...

Page 3

... This section contains a high-level view of the MPC8568E architecture. 1.2.1 e500 Core and Memory Unit The MPC8568E contains a high-performance 32-bit Book E–enhanced e500v2 core that implements Power Architecture. In addition to 36-bit physical addressing, this version of the e500 core includes: • Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. • ...

Page 4

... The local address map is supported by eight local access windows that define mapping within the local 36-bit (64-Gbyte) address space. The MPC8568E can be made part of a larger system address space through the mapping of translation windows. This functionality is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation windows are provided ...

Page 5

... IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA- single pass of the data. The version of the SEC used in the MPC8568E is specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i. ...

Page 6

... The MPC8568E supports DDR SDRAM and DDR2 SDRAM. The memory interface controls main memory accesses and provides for a maximum of 16 Gbytes of main memory. The MPC8568E supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbits, 2 Gbits and 4 Gbits. Four chip select signals support MPC8568E/MPC8567E PowerQUICC III™ ...

Page 7

... The MPC8568E supports bank sizes from 64 Mbytes to 4 Gbytes. Nine column address strobes (MDM[0:8]) are used to provide byte selection for memory bank writes. The MPC8568E can be configured to retain the currently active SDRAM page for pipelined burst accesses. ...

Page 8

... MPC8568E Overview 1.2.9 High Speed I/O Interfaces The MPC8568E supports two high-speed I/O interface standards: serial RapidIO and PCI Express. It can be configured as x1/x4 SRIO and 1x/2x/4x PCI Express simultaneously with the following limitation: • Both SRIO and PCI-Express are limited to use the same clock and are limited to 2.5G. ...

Page 9

... FIFOs are supported for both the transmitter and the receiver. The MPC8568E local bus controller (LBC) port allows connections with a wide variety of external memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be programmed separately to access different types of devices ...

Page 10

... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8568E. This device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...

Page 11

... Core supply voltage PLL supply voltage Core power supply for SerDes transceiver Pad power supply for SerDes transceiver DDR and DDR2 DRAM I/O voltage MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 2 C, and JTAG signals Table 3. Absolute maximum ratings are stress ratings only, and by more than 0 ...

Page 12

... DDR and DDR2 DRAM signals DDR and DDR2 DRAM reference Three-speed Ethernet signals Local bus signals PCI, DUART, SYSCLK, system control and power management, I Junction temperature range Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8568E. B/G/L/T/OV DD B/G/L/T/OV B/G/L/T/ GND – 0.3 V ...

Page 13

... The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT[1] signal at reset. 2.2 Power Sequencing The MPC8568E requires its power rails to be applied in specific sequence in order to ensure proper device operation. These requirements are as follows for power up ...

Page 14

... MHz 533 MHz 33 MHz, 32b 66 MHz, 32b Local Bus 133 MHz, 32b 33 MHz PCI 66 MHz SRIO 4x, 3.125G MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev NOTE Table 5. MPC8568E Power Dissipation QE Frequency Typical 65°C Typical 105°C 400 8.7 400 8.9 400 11 ...

Page 15

... Note: This is the power for each individual interface. The power must be calculated for each interface being utilized. 4 Input Clocks 4.1 System Clock Timing Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8568E. At recommended operating conditions (see Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle MPC8568E/MPC8567E PowerQUICC III™ ...

Page 16

... The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. 4.2 PCI Clock Timing Table 8 provides the PCI clock (PCI_CLK) AC timing specifications for the MPC8568E. At recommended operating conditions (see Parameter/Condition PCI_CLK frequency PCI_CLK cycle time ...

Page 17

... For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no higher than 167 MHz 4.6 Other Input Clocks For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Min f — ...

Page 18

... Input hold time for all POR configs (including PLL config) with respect to negation of HRESET Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Notes: 1. SYSCLK is the primary clock input for the MPC8568E. Table 11 provides the PLL lock times. Parameter/Condition Platform PLL lock times ...

Page 19

... DDR SDRAM component(s) when GV (typ Table 14. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor . Symbol Min GV 1.7 DD 0.49 × REF ...

Page 20

... This parameter is sampled (peak-to-peak) = 0.2 V. OUT Table 16 provides the current draw characteristics for MV Table 16. Current Draw Characteristics for MV Parameter / Condition Current draw for MV REF 1. The voltage regulator for MV MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Symbol Min V –0 – – ...

Page 21

... The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation the absolute value of t CISKEW 3. Maximum DDR1 frequency is 400 MHz. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Min V — ...

Page 22

... Table 20. DDR SDRAM Output AC Timing Specifications At recommended operating conditions. Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS[n] output setup with respect to MCK MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev MCK ...

Page 23

... DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8568E Integrated Communications Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. ...

Page 24

... Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] MDQS MDQS MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev NOTE t MCK t DDKHMHmax DDKHMH(min) = – ...

Page 25

... This section describes the DC and AC electrical specifications for the DUART interface of the MPC8568E. 7.1 DUART DC Electrical Characteristics Table 21 provides the DC electrical characteristics for the DUART interface. Table 21. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor t MCK t ,t DDKHAS DDKHCS t ,t ...

Page 26

... GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compatible with the IEEE 802.3 standard. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Symbol ...

Page 27

... Output low voltage (LV /TV = Min, IOL = 4.0 mA Input high voltage Input low voltage MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor and Table 24. The potential applied to the input of a GMII, MII, TBI, into a GMII receiver powered from a 2.5-V supply). OH Symbol ...

Page 28

... FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and source clock in GMII fashion. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Symbol ...

Page 29

... RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Ethernet Interface and MII Management Table 25 and Table 26 ...

Page 30

... GMII data TXD[7:0], TX_ER, TX_EN setup time GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK data clock rise time (20%-80%) GTX_CLK data clock fall time (80%-20%) EC_GTX_CLK125 clock rise time (20%-80%) EC_GTX_CLK125 clock fall time (80%-20%) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Figure 7 and Figure 8. ...

Page 31

... At recommended operating conditions with L/TV Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise (20%-80%) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor of 3.3 V ± 5%. DD Symbol t /t ...

Page 32

... Figure 11 shows the GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER 8.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev 3.3 V ± 5 Symbol 2 t GRXF (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

Page 33

... MII receive AC timing specifications. Table 30. MII Receive AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor of 3.3 V ± 5 Symbol 2 ...

Page 34

... Output Figure 14 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev 3.3 V ± 5 Symbol t MRDVKH t MRDXKH ...

Page 35

... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. Guaranteed by design. Figure 15 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor of 3.3 V ± 5 Symbol ...

Page 36

... For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. Figure 16 shows the TBI receive AC timing diagram. PMA_RX_CLK1 RCG[9:0] PMA_RX_CLK0 MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev 3.3 V ± 5 Symbol t TRX ...

Page 37

... RGMII and RTBI AC timing specifications. Table 34. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LV Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) 3 Clock period duration MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Min t 7.5 TRR t ...

Page 38

... EC_GTX_CLK125 is used to generate GTX_CLK for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle can be loosen from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC GTX_CLK. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev 2.5 V ± 5%. ...

Page 39

... Table 35. RMII Transmit AC Timing Specifications At recommended operating conditions with LV Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] ...

Page 40

... REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev 3.3 V ± 5 Symbol t RMTDX ...

Page 41

... CRS_DV RX_ER 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor of 3.3 V ± 5 Symbol ...

Page 42

... The symbol this case, represents the OV IN 8.3.2 MII Management AC Electrical Characteristics Table 38 provides the MII management AC timing specifications. Table 38. MII management AC timing specifications Parameters MDC frequency MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Table 37. Symbol Min OV 3. ...

Page 43

... MDC to MDIO data valid t MDKHDV time – Max delay). Figure 22 shows the MII management AC timing diagram. Figure 22. MII Management Interface Timing Diagram MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Min t 400 MDC t ...

Page 44

... High-level output voltage (BV = min –1 mA Low-level output voltage (BV = min mA Note: 1. The symbol this case, represents the BV IN MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Symbol Min Max –0.3 0 — ±5 ...

Page 45

... LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals Guaranteed by design. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Section 23.1, “Clock Ranges.” DD Symbol ...

Page 46

... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between DD complementary signals at BV /2. 8. Guaranteed by design. Figure 23 provides the AC test load for the local bus. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Symbol Min t 7 ...

Page 47

... BV Table 43. Local Bus Timing Parameters—PLL Bypassed Parameter Local bus cycle time Local bus duty cycle MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor = 50 Ω Figure 23. Local Bus AC Test Load ...

Page 48

... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Guaranteed by characterization. 9. Guaranteed by design. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Symbol ...

Page 49

... In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of of the internal clock and are captured at falling edge of the internal clock with the exception of LGTA/LUPWAIT (which is captured on the rising edge of the internal clock). MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor t LBKHKT t ...

Page 50

... LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 ...

Page 51

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor t t LBKLOX1 LBKLOV1 t ...

Page 52

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 ...

Page 53

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 29. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor t t LBKLOX1 LBKLOV1 t ...

Page 54

... This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface of the MPC8568E. 10.1 JTAG DC Electrical Characteristics Table provides the DC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8568E. Table 44. JTAG DC Electrical Characteristics Parameter Output high voltage Output low voltage ...

Page 55

... Figure 30. AC Test Load for the JTAG Interface Figure 31 provides the JTAG clock input timing diagram. JTAG External Clock Figure 31. JTAG Clock Input Timing Diagram Figure 32 provides the TRST timing diagram. TRST MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3). 2 Symbol t JTKLDZ t ...

Page 56

... Input high voltage level Input low voltage level Low level output voltage Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 × OV 0.9 × OV (max) DD MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev JTDVKH t JTKLDV t ...

Page 57

... Parameter Capacitance for each I/O pin Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8568E PowerQUICC III Integrated Communications Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines ...

Page 58

... Figure 35 shows the AC timing diagram for the I SDA t I2CL SCL t I2SXKL S MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Electrical Specifications (continued) ± of 3.3V 5%. All values refer (first two letters of functional block)(signal)(state) (reference)(state) for outputs. For example, t ...

Page 59

... PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8568E. 12.1 PCI DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the PCI interface. Table 48. PCI DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current ...

Page 60

... AC test load for PCI. Output Figure 37 shows the PCI input AC timing conditions. CLK Input Figure 37. PCI Input AC Timing Measurement Conditions MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Symbol t PCRHFV for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) , reference (K) going to the high (H) state or setup time ...

Page 61

... Figure 38. PCI Output AC Timing Measurement Condition 13 High-Speed Serial Interfaces (HSSI) The MPC8568E features one Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. It can be used for PCI Express and/or Serial RapidIO data transfers. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane’ ...

Page 62

... TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges OD MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev – V The V SD_RX SD_RX ...

Page 63

... AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V ...

Page 64

... SD_REF_CLK Figure 40. Receiver of SerDes Reference Clocks 13.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8568E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • ...

Page 65

... SD_REF_CLK SD_REF_CLK Figure 42. Differential Reference Clock Input DC Requirements (External AC-Coupled) 400 mV SD_REF_CLK SD_REF_CLK Figure 43. Single-Ended Reference Clock Input DC Requirements MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Input Amplitude or Differential Peak < Input Amplitude or Differential Peak < < 8 SD_REF_CLK Input Amplitude High-Speed Serial Interfaces (HSSI) < ...

Page 66

... MPC8568 SerDes reference clock receiver requirement provided in this document. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev NOTE below are for conceptual reference only. Due to the ...

Page 67

... CLK_Out Clock Driver Clock Driver CLK_Out 10 nF Figure 45. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK Clock driver vendor dependent source termination resistor SD_REF_CLK 100 Ω ...

Page 68

... LVPECL CLK Driver Chip CLK_Out R1 Clock Driver Clock Driver CLK_Out R1 Figure 46. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK Figure 46 MPC8568E 50 Ω ...

Page 69

... Figure 47 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8568E SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33 Ω Clock Driver CLK_Out Figure 47. Single-Ended Connection (Reference Only) 13 ...

Page 70

... Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. 14 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8568E. 14.1 DC Requirements for PCI Express SD_REF_CLK and ...

Page 71

... D+/D- TX Output TX-RISE TX-FALL Rise/Fall Time MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Min Nom Max Units 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations ...

Page 72

... Electrical Idle ordered set T Maximum time to TX-IDLE-TO-DIFF-DATA transition to valid TX specifications after leaving an Electrical idle condition RL Differential TX-DIFF Return Loss MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Min Nom Max Units — — TX-CM-ACp V TX-CM-DC See Note 2 0 — ...

Page 73

... The exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Min ...

Page 74

... The parameters are specified at the component pins. Table 52. Differential Receiver (RX) Input Specifications Symbol Parameter UI Unit Interval V Differential RX-DIFFp-p Peak-to-Peak Output Voltage MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev NOTE Min Nom Max Units 399.8 400 400. 0.175 — ...

Page 75

... Powered Down RX-HIGH-IMP-DC DC Input Impedance V Electrical Idle RX-IDLE-DET-DIFFp-p Detect Threshold T Unexpected RX-IDLE-DET-DIFF- Electrical Idle ENTERTIME Enter Detect Threshold Integration Time MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Min Nom Max Units 0.4 — — UI — — 0.3 UI — — ...

Page 76

... Receiver based on some adequate combination of system simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Min ...

Page 77

... The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor NOTE Figure 51) ...

Page 78

... This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8568E, for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1 ...

Page 79

... The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal – B) Volts Volts Volts Figure 52. Differential Peak-Peak Voltage of Transmitter or Receiver MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Min Typical Max Units — 10(8) — ...

Page 80

... It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair not exceed 1.25 GB 2.50 GB and 3.125 GB. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 81

... Total Jitter Multiple Output skew Unit Interval Table 56. Short Run Transmitter AC Timing Specifications—3.125 GBaud Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Range Symbol Min Max V –0.40 2.30 ...

Page 82

... Unit Interval Table 58. Long Run Transmitter AC Timing Specifications—2.5 GBaud Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Range Symbol Min Max S — 1000 ...

Page 83

... Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized. V max DIFF V min DIFF 0 -VDIFF min -VDIFF max 0 Figure 53. Transmitter Output Compliance Mask MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Range Symbol Min Max V –0.40 2. 800 1600 ...

Page 84

... Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev ...

Page 85

... Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Range ...

Page 86

... Receiver Input Compliance Mask shown in receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ω +/– 5% differential resistive load. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Frequency (Table ...

Page 87

... Eye Template Measurements For the purpose of eye template measurements, the effects of a single-pole high pass filter with point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor A ...

Page 88

... Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in is then added to the signal and the test load is replaced by the receiver being tested. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev -12 ...

Page 89

... Timers This section describes the DC and AC electrical specifications for the timers of the MPC8568E. 16.1 Timers DC Electrical Characteristics Table 65 provides the DC electrical characteristics for the MPC8568E timers pins, including TIN, TOUT, TGATE and RTC_CLK. Table 65. Timers DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...

Page 90

... This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8568E. 17.1 PIC DC Electrical Characteristics Table 67 provides the DC electrical characteristics for the external interrupt pins of the MPC8568E. Characteristic Input high voltage Input low voltage Input current Output low voltage ...

Page 91

... SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8568E. 18.1 SPI DC Electrical Characteristics Table 69 provides the DC electrical characteristics for the MPC8568E SPI. Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 18 ...

Page 92

... MPC8568E. 19.1 TDM/SI DC Electrical Characteristics Table 71 provides the DC electrical characteristics for the MPC8568E TDM/SI. Table 71. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Table t NEIXKH t NEKHOV t NIIXKH t ...

Page 93

... AC test load for the TDM/SI. Output Figure 61 represents the AC timing from reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Condition V — ...

Page 94

... UTOPIA input and output AC timing specifications. Characteristic Utopia outputs—Internal clock delay Utopia outputs—External clock delay Utopia outputs—Internal clock High Impedance Utopia outputs—External clock High Impedance MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev SEIXKH t SEKHOV ...

Page 95

... Figure 63 shows the Utopia timing with external clock. UtopiaCLK (input) t UEIVKH Input Signals: Utopia Output Signals: Utopia Figure 63. Utopia AC Timing (External Clock) Diagram MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol t UIIVKH t UEIVKH t UIIXKH t UEIXKH ...

Page 96

... BISYNC, transparent and synchronous UART of the MPC8568E. 21.1 HDLC, BISYNC, Transparent and Synchronous UART DC Electrical Characteristics Table 75 provides the DC electrical characteristics for the MPC8568E HDLC, BISYNC, Transparent and Synchronous UART protocols. Table 75. HDLC, BiSync, Transparent and Synchronous UART DC Electrical Characteristics Characteristic Output high voltage ...

Page 97

... HIKHOX high state (H) until outputs (O) are invalid (X). Figure 65 provides the AC test load. Output MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor HDLC, BISYNC, Transparent and Synchronous UART Symbol t HIKHOX t HEKHOX ...

Page 98

... Serial CLK (output) Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable Figure 67. AC Timing (Internal Clock) Diagram MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev Table t HEIXKH t HEKHOV t ...

Page 99

... Module height Solder Balls Ball diameter (typical) 22.2 Mechanical Dimensions of the MPC8568E FC-PBGA Figure 68 shows the top view, bottom and side view of the MPC8568E 1023 FC-PBGA package. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 33 mm × 1023 1 mm 2.23 – ...

Page 100

... Package and Pinout 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. All dimensions are symmetric across the package center lines, unless dimensioned otherwise. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 100 Figure 68. Top, Bottom, Side Views Freescale Semiconductor ...

Page 101

... PC[19] IIC2_SDA PD[28] UART_SOUT[1] PD[29] UART_RTS[1] PD[30] UART_CTS[1] PD[31] UART_SIN[1] This applies to both MPC8568E and MPC8568E. Please note that for DUART1, there are two options. DUART0 is multiplexed with PCI Req/Grant pins. PCI_REQ[3] UART_CTS[0] PCI_REQ[4] UART_SIN[0] PCI_GNT[3] UART_RTS[0] PCI_GNT[4] UART_SOUT[0] For MPC8568E, GPIO is multiplexed with the TSEC2 interface: ...

Page 102

... Package and Pinout TSEC2_RXD[7:0] GPIN[0:7] Other muxing includes: LCS[5] DMA_DREQ[2] LCS[6] DMA_DACK[2] LCS[7] DMA_DDONE[2] Table 79 provides the pin-out listing for the MPC8568E 1023 FC-PBGA package. Signal PCI_AD[31:0] PCI_C_BE[3:0] PCI_GNT[4:1] PCI_GNT0 PCI_IRDY PCI_PAR PCI_PERR PCI_SERR PCI_STOP PCI_TRDY PCI_REQ[4:1] PCI_REQ[0] PCI_CLK PCI_DEVSEL PCI_FRAME ...

Page 103

... LWE[1] LWE[2] LWE[3] LGPL0 LGPL1 LGPL2 MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number D21, G20, C17, D14, E10, C6, F4, C3, C10 C21, G21, C18, D15, F10, C7, F5, D3, B10 K7, H7, L7, J8, K8, L10, H9, K9, H10, G10, L6, K10, ...

Page 104

... EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] TSEC1_TXD[7] TSEC1_TXD[6:1] TSEC1_TXD[0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 104 Package Pin Number J25 C25 F32 C31 C27, C26, D25 A28 A27 DMA AM27 AK28 ...

Page 105

... SD_TX[0:7] SD_TX[0:7] SD_PLL_TPD SD_RX_CLK SD_RX_FRM_CTL Reserved Reserved SD_REF_CLK SD_REF_CLK MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number AJ11 AC13 AL12 AC14, AD15, AB14, AH15, AD14, AH17, AE15, AC15 AM16 AJ15, AJ17, AF13, AK17, AH16, AG17 ...

Page 106

... PF[11:19] PF[20] PF[21:22] PF[23:31] HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 106 Package Pin Number QUICC Engine M1, M2, M5, M4 M6, M7, M8, N5, M10, N1, M11, M9, P1, N9, N7, R6, R2, P7, P5, R4, P3, P11, P10, P9, R8, R7, R5, R3, R1, T2 T1, R11, R9, T6, T5, T4, T3, U10, T9, T8, T7, U5, ...

Page 107

... SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number Debug AL29 AM29 AK29, AJ29 AM28, AL28, AK27 AJ28 AF18 Clock AH20 AK22 JTAG ...

Page 108

... GND SCOREGND XGND OVDD LVDD TVDD MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 108 Package Pin Number Power and Ground Signals A23, A26, A32, B3, B6, B9, B12, B18, B21, B23, B24, B25, B26, B27, C15, C24, D5, D8, D11, D17, D20, D23, D24, D28, E13, E14, E24, E31, F3, F7, ...

Page 109

... DD_PLAT AV DD_SRDS AGND_SRDS SENSEVDD MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number B2, B5, B8, B11, B17, B20, C14, D4, D7, D10, D16, D19, D22, E12, E15, F2, F6, F21, G9, G17, G18, H4, H11, H14, H20, J3, J6, J9, K13, L2, L5, L8, L11 ...

Page 110

... Package and Pinout Table 78. MPC8568E Pinout Listing (continued) Signal SENSEVSS MVREF SD_IMP_CAL_RX SD_IMP_CAL_TX SD_PLL_TPA MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 110 Package Pin Number M16 Analog Signals A24 K32 AA28 R30 Power Pin Type Notes Supply — — ...

Page 111

... Independent supplies derived from board VDD. 27. Recommend a pull-up resistor (~1 K.) be placed on this pin to OV 29. The following pins must NOT be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP, PA[5] MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number Ratio.” ...

Page 112

... PCI_GNT0 PCI_IRDY PCI_PAR PCI_PERR PCI_SERR PCI_STOP PCI_TRDY PCI_REQ[4:1] MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 112 Package Pin Number Termination.” Table 79. MPC8567E Pinout Listing Package Pin Number PCI AE19, AG20, AF19, AB20, AC20, AG21, AG22, AB21, AF22, AH22, AE22, AF20, AB22, AE20, ...

Page 113

... MCS[0:3] MCK[0:5] MCK[0:5] MODT[0:3] MDIC[0:1] LAD[0:31] LDP[0:3] LA[27] LA[28:31] LALE MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number AC17 AM26 AK23 AE21 AB19 DDR SDRAM Memory Interface B22, C22, E20, A19, C23, A22, A20, C20, G22, E22, ...

Page 114

... LCKE LCLK[0:2] LSYNC_IN LSYNC_OUT DMA_DACK[0] DMA_DREQ[0] DMA_DDONE[0] UDE MCP IRQ[0:7] IRQ_OUT GPIN[0:7] GPOUT[0:7] MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 114 Package Pin Number L27 M27, H32, J28, J30, B31 G25 C29 A30 H30 E28 E32 G27 E30 J27 ...

Page 115

... PA[0:4] PA[5] PA[6:31] PB[4:31] PC[0:31] PD[4:31] PE[5:7] PE[8:10] PE[11:19] PE[20] PE[21:23] MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number interface AE32 AD32 SerDes L30, M32, N30, P32, U30, V32, W30, Y32 L29, M31, N29, P31, U29, V31, W29, Y31 P26, R24, T26, U24, W24, Y26, AA24, AB26 ...

Page 116

... SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 116 Package Pin Number AJ1 AH2, AM2, AE9, AH5, AL1, AD9, AL4 AG9 AF10, AK7, AJ6 AH7, AF9, AJ7, AJ5, AF7, AG8, AG7, AM5, AK5 ...

Page 117

... Table 79. MPC8567E Pinout Listing (continued) Signal L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND SCOREGND XGND MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number AJ19 AH31 AJ31 Thermal Management AB30 AB31 Power Management AK21 Power and Ground Signals ...

Page 118

... AV DD_LBIU AV DD_PCI AV DD_CE MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 118 Package Pin Number N2, N6, N10, P4, P8, T10, U2, U6, V4, V8, Y10, AA2, AA6, AB4, AB8, AC19, AC21, AD10, AD23, AE2, AE6, AE27, AE31, AG4, AG19, AG23, AG25, AH21, AH28, AH30, AH32, AJ2, AK4, AK25, AK31, ...

Page 119

... AV DD_CORE AV DD_PLAT AV DD_SRDS AGND_SRDS SENSEVDD SENSEVSS MVREF SD_IMP_CAL_RX SD_IMP_CAL_TX SD_PLL_TPA Reserved Reserved MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number AM24 AM20 R29 R31 M17 M16 Analog Signals A24 K32 AA28 R30 Reserved Pins AE17, AH12, AL13, AL11, AK13, AH13, AG11, ...

Page 120

... Independent supplies derived from board VDD. 27. Recommend a pull-up resistor (~1 K.) be placed on this pin to OV 29. The following pins must NOT be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP, PA[5]. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 120 Package Pin Number Ratio.” ...

Page 121

... Must be high during HRESET recommended to leave the pin open during HRESET since it has internal pullup resistor. 47. Must be pulled down with 4.7-kΩ resistor. 48. This pin must be left no connect 23 Clocking This section describes the PLL configuration of the MPC8568E. Note that the platform clock is identical to the core complex bus (CCB) clock. 23.1 Clock Ranges ...

Page 122

... For specifications on the PCI_CLK, refer to the PCI 2.2 Specification. Binary Value of CCB:SYSCLK Ratio LA[28:31] Signals 0000 0001 0010 0011 0100 MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 122 Maximum Processor Core Frequency 800, 1000, 1333 MHz Min 166 Maximum Processor Core Frequency 800, 1000, 1333 MHz Min 25 Table 83 ...

Page 123

... Table 85. QE Clock Multiplier cfg_ce_pll[0:4] Binary Value of PA[0:4] Signals 0_0000 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 83. CCB Clock Ratio (continued) Binary Value of LA[28:31] Signals 5:1 1101 6:1 1110 Reserved 1111 Table 84. e500 Core to CCB Clock Ratio ...

Page 124

... Table 86. Frequency Options of SYSCLK with Respect to Memory Bus Speeds CCB clock to SYSCLK Ratio 16. 400 20 333 500 MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 124 Binary Value of cfg_ce_pll[0:4] PA[0:4] Signals 8 1_1000 9 1_1001 10 1_1010 11 1_1011 12 1_1100 13 1_1101 14 1_1110 ...

Page 125

... Thermal Management Information This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor × ...

Page 126

... Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, and MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 126 Figure 69 ...

Page 127

... MPC8568E to function in various environments. 24.2.1 Recommended Thermal Model For system thermal modeling, the MPC8568E thermal model without a lid is shown in substrate is modeled as a block 33x33x1.18 mm with an in-plane conductivity of 24 W/mK and a through-plane conductivity of 0.92 W/mK. The solder balls and air are modeled as a single block 33x33x0.58 mm with an in-plane conductivity of 0.034 W/mK and a through plane conductivity of 12.2 W/mK ...

Page 128

... Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 69). Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 128 Radiation Convection ...

Page 129

... S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease 20 30 ...

Page 130

... Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 130 888-246-9050 Section 23.2, “CCB/SYSCLK PLL Ratio.” ...

Page 131

... Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. MPC8568E system, and the device itself requires a clean, tightly regulated source of power. Therefore recommended that the system designer place at least one decoupling capacitor at each V ...

Page 132

... GND pins of the device 25.6 Pull-Up and Pull-Down Resistor Requirements The MPC8568E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins 2 including I C pins and MPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 75 ...

Page 133

... Refer to the PCI 2.2 specification for all pull-ups required for PCI. 25.7 Configuration Pin Muxing The MPC8568E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins. These pins are generally used as output only pins in normal operation. ...

Page 134

... IC). Regardless of the numbering, the signal placement recommended in Figure 75 is common to all known emulators. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 134 allows the COP to independently assert HRESET or TRST, while adds many benefits—breakpoints, watchpoints, register and memory Figure 75 ...

Page 135

... Use a NOR gate with sufficient drive strength to drive two inputs. 25.9 Guidelines for High-Speed Interface Termination 25.9.1 Unused output Any of the outputs that are unused should be left unconnected. These signals are: • SD_TX[7:0] MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor SRESET HRESET HRESET 13 SRESET 11 ...

Page 136

... PE[8:10]. Software must disable this mode through DEVDISR[SRIO] or DEVDISR[PCIE] accordingly during software initialization. 26 Ordering Information Please contact your local Freescale sales office or regional marketing team for order information. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 136 DD_SRDS NOTE ...

Page 137

... Qualified Device Number 8568, 8567 Security Blank: No Security E: With Security Temperature Blank 105C C: -45(Ta) - 105C MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Figure 76. MPC856Xxxxxxx ATWLYYWW MMMMM CCCCC FC-PBGA MPC 856x ANG J A Figure 77. MPC8568E Part Number Decoder ...

Page 138

... Document Revision History 27 Document Revision History Table 88 provides a revision history for the MPC8568E hardware specification. Rev Date Number 0 05/2009 Initial public release. MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 138 Table 88. Document Revision History Substantive Change(s) Freescale Semiconductor ...

Page 139

... THIS PAGE INTENTIONALLY LEFT BLANK MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Document Revision History 139 ...

Page 140

... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8568EEC Rev. 0 05/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...