mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 123

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

23.3
Table 84
clock. This ratio is determined by the binary value of LBCTL, LALE and LGPL2 at power up, as shown
in
23.4
The QE clock is defined by a multiplier and divisor applied to the SYSCLK input signal, as shown in the
following equation:
The multiplier and divisor is determined by the binary value of PA[0:4] at power up.
Freescale Semiconductor
Table
LA[28:31] Signals
84.
describes the clock ratio between the e500 core complex bus (CCB)platform and the e500 core
e500 Core PLL Ratio
Binary Value of
Binary Value of
LGPL2 Signals
QE/SYSCLK PLL Ratio
LBCTL, LALE,
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
0101
0110
0111
000
001
010
011
QE clock = SYSCLK * cfg_ce_pll[0:4].
Binary Value of
PA[0:4] Signals
0_0000
0_0001
0_0010
0_0011
0_0100
0_0101
0_0110
0_0111
e500 core:CCB Clock Ratio
CCB:SYSCLK Ratio
Table 85. QE Clock Multiplier cfg_ce_pll[0:4]
Table 84. e500 Core to CCB Clock Ratio
Table 83. CCB Clock Ratio (continued)
Reserved
Reserved
4:1
9:2
3:2
cfg_ce_pll[0:4]
5:1
6:1
Reserved
16
2
3
4
5
6
7
LA[28:31] Signals
Binary Value of
LGPL2 Signals
LBCTL, LALE,
Binary Value of
Binary Value of
PA[0:4] Signals
100
101
110
111
1_0000
1_0001
1_0010
1_0011
1_0100
1_0101
1_0110
1_0111
1101
1110
1111
e500 core:CCB Clock Ratio
cfg_ce_pll[0:4]
CCB:SYSCLK Ratio
16
17
18
19
20
21
22
23
Reserved
Reserved
20:1
2:1
5:2
3:1
7:2
Clocking
123