mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 23

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
At recommended operating conditions.
MCS[n] output hold with respect to MCK
MCK to MDQS Skew
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to
MDQS
MDQS preamble start
MDQS epilogue end
Note:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
7. Maximum DDR1 frequency is 400 MHz
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
outputs (A) are setup (S) or output valid time. Also, t
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock
adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set
to the same adjustment value. See the MPC8568E Integrated Communications Processor Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
symbolizes DDR timing (DD) for the time t
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
follows the symbol conventions described in note 1. For example, t
Table 20. DDR SDRAM Output AC Timing Specifications (continued)
533 MHz
400 MHz
333 MHz
533 MHz
400 MHz
333 MHz
533 MHz
400 MHz
333 MHz
Symbol
t
t
t
t
t
t
t
t
DDKHDS,
DDKHDX,
DDKHMH
DDKHCX
DDKHMP
DDKHME
DDKLDS
DDKLDX
MCK
DDKLDX
memory clock reference (K) goes from the high (H) state until
1
symbolizes DDR timing (DD) for the time t
–0.5 × t
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
1.48
1.95
2.40
–0.6
–0.6
Min
538
700
900
538
700
900
MCK
– 0.6
–0.5 × t
DDKHMH
DDKHMH
Max
0.6
0.6
—
—
—
—
—
—
—
—
—
MCK
describes the DDR timing
+0.6
can be modified through
DDKHMP
DDR and DDR2 SDRAM
MCK
Unit
memory clock
ns
ns
ps
ps
ns
ns
follows the
Notes
3
7
4
5
7
5
7
6
6
for
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