mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 134

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in
Figure 75
allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted.
The COP header shown in
Figure 75
adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
There is no standardized way to number the COP header shown in
Figure
75; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 75
is common to all known emulators.
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
134
Freescale Semiconductor