mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 18

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

RESET Initialization
5
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8568E.
SDRAM component(s).
Table 11
6
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8568E. Note that DDR SDRAM is GV
18
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
Notes:
1. SYSCLK is the primary clock input for the MPC8568E.
RESET Initialization
DDR and DDR2 SDRAM
provides the PLL lock times.
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
Platform PLL lock times
QE PLL lock times
CPU PLL lock times
PCI PLL lock times
Local bus PLL
Table 10
Parameter/Condition
Parameter/Condition
provides the RESET initialization AC timing specifications for the DDR
Table 10. RESET Initialization Timing Specifications
Table 11. PLL Lock Times
DD
(typ) = 2.5 V and DDR2 SDRAM is GV
Min
—
—
—
—
—
Min
100
100
Max
—
100
100
100
100
100
3
4
2
Max
—
—
—
—
—
5
Unit
μs
μs
μs
μs
μs
Freescale Semiconductor
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
Notes
DD
Unit
μs
μs
—
—
—
—
—
(typ) = 1.8 V.
Notes
—
—
1
1
1
1