mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 58

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

I
Figure 30
Figure 35
58
At recommended operating conditions with OV
2
Capacitive load for each bus line
Note:
1.The symbols used for timing specifications herein follow the pattern t
2. As a transmitter, the MPC8568 provides a delay time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4.The requirements for I
C
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the STOP condition (P) reaching the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup time.
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP condition.
When the MPC8568 acts as the I
load on SCL and SDA are balanced, the MPC8568 would not cause unintended generation of START or STOP condition.
Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay
time is required for the MPC8568 as transmitter, application note AN2919 referred to in note 4 below is recommended.
the I
SDA
SCL
2
C Frequency Divider Ratio for SCL
provides the AC test load for the I
shows the AC timing diagram for the I
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
S
(first two letters of functional block)(reference)(state)(signal)(state)
I2DXKL
t
t
I2CL
I2SXKL
2
has only to be met if the device does not stretch the LOW period (t
C frequency calculation must be followed. Refer to Freescale application note AN2919, Determining
Output
Parameter
Table 47. I
I2SXKL
2
I2C
C bus master while transmitting, the MPC8568 drives both SCL and SDA. As long as the
symbolizes I
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 35. I
t
DD
I2DXKL
2
of 3.3V
C AC Electrical Specifications (continued)
Figure 34. I
t
I2DVKH
Z
0
±
2
= 50 Ω
t
I2CH
C timing (I2) for the time that the data with respect to the START condition
5%. All values refer to V
2
2
C.
C Bus AC Timing Diagram
2
t
I2SXKL
2
C bus.
C AC Test Load
for outputs. For example, t
Sr
(first two letters of functional block)(signal)(state) (reference)(state)
t
I2SVKH
IH
Symbol
R
(min) and V
L
C
= 50 Ω
b
1
I2C
IL
(max) levels (see
t
clock reference (K) going to the high
I2PVKH
OV
I2CL
t
Min
I2KHKL
I2DVKH
—
DD
) of the SCL signal.
/2
symbolizes I
Freescale Semiconductor
I2PVKH
P
Table
Max
400
IH
46).
symbolizes I
min of the SCL
2
C timing (I2)
S
Unit
pF
I2C
2
for
C