mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 49

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mpc8568e

Manufacturer Part Number
mpc8568e
Description
Mpc8568e Powerquicc Iii Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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LA[27:31]/LBCTL/LBCKE/LOE/
Internal launch/capture clock
LSDA10/LSDWE/LSDRAS/
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
Output Signals:
Input Signals:
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of
of the internal clock and are captured at falling edge of the internal clock
with the exception of LGTA/LUPWAIT (which is captured on the rising
edge of the internal clock).
Input Signal:
LUPWAIT
LAD[0:31]
LCLK[n]
LGTA
LALE
Figure 25. Local Bus Signals (PLL Bypass Mode)
t
LBKHKT.
In this mode, signals are launched at the rising edge
t
LBKLOV1
t
LBKLOV2
NOTE
t
t
LBKLOV3
LBKLOV4
t
LBKHKT
t
LBIVKH1
t
LBOTOT
t
t
LBKLOX1
LBKLOX2
t
LBIXKH1
t
LBIVKL2
t
LBIXKL2
Local Bus
t
t
LBKLOZ1
LBKLOZ2
49

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