ucb1500 NXP Semiconductors, ucb1500 Datasheet - Page 23

• Manufacturer Part Number: ucb1500
• Description: Pci To Ac97 Bridge/host Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 07443
Product specification
8.1.7 [0016]: Transmit DMA #1 FIFO count register
8.1.8 [0017]: Transmit DMA #1 command register
Table 28: Transmit DMA #1 FIFO count register bit description
Table 29: Transmit DMA #1 Command Register bit description
Bit
15(r)
14
13-7
6-0(r)
Bit
15-14
13
12(r)
11(r)
10-9
8(r)
7
6
5(w)
Description
Open PCI Master Cycle (for internal use only)
This bit is set if there is an outstanding PCI master cycle as a result of PCI retry
termination by the target. Software should wait for this bit to be cleared when
initiating another DMA transfer right after an aborted DMA transfer.
DTP Invalid Bit Mask
If this bit is set to ‘1’, the transmit DMA engine will transmit data from the current
descriptor fetched even if the invalid bit set.
Reserved.
Transmit DMA #1 FIFO count (for internal use only)
Number of bytes to be transmitted that is still in the internal 64-byte FIFO.
Description
Threshold level
Specifies the level at which data is transferred from the memory to the 64-byte
transmit FIFO. The recommended setting for this register is 32 bytes threshold.
Reserved.
Transmit DMA #1 Abort status
This read-only bit is set if the transmit channel has been aborted as a result of a
PCI, D-channel contention or a software abort. The condition is cleared by
writing a ‘1’ to the transmit DMA clear abort bit, bit 5 of this register.
Transmit DMA #1 DT full
This read only bit is set whenever all the transmit descriptors for DMA #1 have
been used, and the transmit DMA is done. If descriptor table is setup as a
circular queue, this bit does not become set. Writing a 1 to this register clears
this status bit.
Reserved.
Transmit-DMA #1 active status
If set, DT of transmit DMA #1 is currently transmitting data.
Transmit DMA #1 enable
Must be set to 1.
Reserved.
Clear Abort
Set this bit to 1 to clear abort status initiated by setting the transmit abort bit. This
bit clears the PCI abort and transmit abort condition. This is a write only bit and it
automatically goes back to 0 after one clock.
00 = 16 bytes, data will be transferred from memory as soon as there is at
least 16 bytes of free space in the transmit FIFO.
01 = 32 bytes
10 = 48 bytes
11 = 60 bytes
Rev. 03 — 7 July 2000
PCI to AC97 bridge/host controller
© Philips Electronics N.V. 2000. All rights reserved.
UCB1500
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