ucb1500 NXP Semiconductors, ucb1500 Datasheet - Page 37

• Manufacturer Part Number: ucb1500
• Description: Pci To Ac97 Bridge/host Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 07443
Product specification
8.6.10 [00c9]: AC97 command/GPIO control and status register
8.6.11 [00ca]: AC97 command data register
Table 55: AC97 command/GPIO control and status register bit description
Table 56: AC97 command data register bit description
Bit
15-10
9
8
7
6
5-3
2
1
0
Bit
15-0
Description
Reserved.
Valid GPIO data
Reads to this register will return a “1” if there is valid read data from the codec
connected to AC97 channel #0 in register CDh. Writing a “1” to this bit will clear
the status.
AC97 command GPIO enable
Writing a 1 to this bit issues GPIO data to slot 12. Data is specified in register
CDh. When enabled, specified value will be transmitted repeatedly during slot 12
timeslot. Writing a “0” to this bit will disable GPIO transmit (slot12 = ‘h00000,
tag big = invalid).
Slotreq #1 enable
If “1”, UCB1500 will monitor the slotreq bits from codec enabled on DMA
channel #1. Used for 'On demand” sample transport scheme.
Slotreq #0 enable
If “1”, UCB1500 will monitor the slotreq bits from codec enabled on DMA
channel #0. Used for 'On demand” sample transport scheme.
Power-up Sync counter
Register counts the number of audio frame times since AC97 Bit Clock was
restarted. This 3-bit counter counts up to 4, then remains 4 until the next time the
AC97 power down occurs.
BITCLK status
This bit is set if the BITCLK is detected idle for PCLK
approximately 1.4 s. After PCLK
the SDATAOUT and SYNC signals are forced to zero.
Warm AC97 Reset
Writing a “1” to this register will cause UCB1500 to generate a Warm AC97 reset
by driving SYNC HIGH for a minimum of 1 s. Reads to this bit will return a “1”
while power-up is in progress. Warm AC97 reset will only occur if BITCLK is
inactive for at least 1 audio frame. Writes to this bit is ignored if BITCLK is active.
Reserved.
Description
Command data register
This register contains data to be written to the AC97 during write command, and
contains read data from codec during read command. Read data is valid when
register C8h bit 10 is set.
0000 = 0 SYNC frame periods have occurred after power-up.
0001 = 1 SYNC frame periods have occurred after power-up.
0010 = 2 SYNC frame periods have occurred after power-up.
0011 = 3 SYNC frame periods have occurred after power-up.
0100 = 4 SYNC frame periods have occurred after power-up.
0101-1111 = Reserved.
Rev. 03 — 7 July 2000
66 time period has passed, or about 2 s,
PCI to AC97 bridge/host controller
© Philips Electronics N.V. 2000. All rights reserved.
48 period, or
UCB1500
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