isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 21

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
9. Protocol description
ISP1504A1_ISP1504C1_1
Product data sheet
9.1 ULPI references
9.2 Power-On Reset (POR)
9.3 Power-up, reset and bus idle sequence
This following subsections describe the protocol for using the ISP1504x1.
The ISP1504x1 provides a 12-pin ULPI interface to communicate with the link. It is highly
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and
UTMI+ Specification Rev. 1.0 .
An internal POR is generated when REG1V8 rises above V
t
below V
voltage on REG1V8 is generated from V
To give a better view of the functionality,
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR turns to logic 1 and a delay element will add another t
drops to logic 0. If REG1V8 dips from t2 to t3 for > t
generated. If the dip at t4 to t5 is too short, that is, < t
will not react and will remain LOW.
Figure 6
On power-up, the ISP1504x1 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1504x1 de-asserts DIR and outputs 60 MHz on the CLOCK pin. The power-up time
depends on the V
(t
and drives DATA[7:0] with RXCMD values. When DIR is de-asserted, the link must drive
the data bus to a valid level. By default, the link must drive data to LOW. When the
ISP1504x1 initially de-asserts DIR on power-up, the link must ignore all RXCMDs until it
resets the ISP1504x1. Before beginning USB packets, the link must set the RESET bit in
the Function Control register to reset the ISP1504x1. After the RESET bit is set, the
ISP1504x1 will assert DIR until the internal reset completes. The ISP1504x1 will
automatically de-assert DIR and clear the RESET bit when reset has completed. After
every reset, an RXCMD is sent to the link to update USB status information. After this
sequence, the ULPI bus is ready for use and the link can start USB operations.
w(REG1V8_H)
Fig 5. Internal power-on reset timing
startup(o)(CLOCK)
POR(trip)
shows a typical start-up sequence.
t0
. The internal POR pulse will also be generated whenever REG1V8 drops
). Whenever DIR is asserted, the ISP1504x1 drives the NXT pin to LOW
for more than t
t1
CC
t
PORP
supply rise time, the crystal start-up time, and the PLL start-up time
Rev. 01 — 6 August 2007
w(REG1V8_L)
t2
Figure 5
ISP1504A1; ISP1504C1
CC
, and then rises above V
.
t3
t
PORP
shows a possible curve of REG1V8. The
w(REG1V8_L)
w(REG1V8_L)
t4
ULPI HS USB OTG transceiver
POR(trip)
t5
, another POR pulse is
, the internal POR pulse
POR(trip)
for at least
© NXP B.V. 2007. All rights reserved.
004aaa751
PORP
REG1V8
V
POR
POR(trip)
again. The
before it
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